traces on the mobo are running over ground plane, is that adapter 4 layer? That is a scary amount of thin traces close together to be routed without ground. Adding load to the bus attenuates interference picked up from surrounding signals, but also weakens original proper ones so is a double edged sword. There isnt even any decoupling for CPU power near the socket.

I wasnt joking when I said its black magic. "High Speed Digital Design: A Handbook Of Black Magic" https://searchworks.stanford.edu/view/4658028 isnt a meme, and neither is the sequel "High-speed Signal Propagation: Advanced Black Magic" https://searchworks.stanford.edu/view/5427843
eevblog had dr. Johnson on amp hour podcast - An Interview with Dr. Howard Johnson https://theamphour.com/the-amp-hour-77-winsom … eform-wizardry/

Blavius' adapter (green one in photos) is 2-layer only. My adapter (red) is operating in the Z-plane. lol.

Hopefully Sphere's adapter resolves things.

Sphere's current layout is at 6-layer, but I don't think each and every one of the data/address/other lines are necessarily over a ground plane. Should they be?

Interesting that you should mention grounding, I have improved the ground presence in the middle.

Take a reeeeeeeaaalllly close look at this. give it a day or two and if no one points anything out let's prototype this.

-Adjusted a lot of traces on many levels,
-Added j1 option solder bridge
-Added ground plane to top and bottom layer in middle where no vcc3/vcc5 flood was needed.

continued

Examining while bored, I see a few things, small things.

Text on j1 mirrored

Trace on turquoise upper left

Dividing line on blue between floods

Minor stuff that is fine as is, I just think I can do a little better.

It’ll never end 🤣. Look at it enough and you’ll think of something.

Yeah, probably when no new ideas come up after 1 or 2 weeks, that may be the final beta. Unfortunately, nobody else with sufficient PCB layout experience have come forth to review the files.

When OCD is at the helm with projects like these they are never done 🤣. But there comes a point when everything works and it is reasonably tidy that you just decide you are done tinkering with it. And let it lie, or you go mad nit picking every angle, every routing path, etc. usually that point is when it looks good and the changes you are making are well into the whole point of diminishing return realm.

The physical prototype is usually part of the process btw, it will often reveal a few things that we want to change. So whenever you are comfortable, but on my end I’m winding down, feels like it is in a good place. I’ll take another look at it here in a few and upload those final touches but they are insignificant changes. There will be more I’m sure after prototype that you’ll request. That’s usually how it goes.

Depending on how the first prototype looks there may be a second prototype before we decide to call it v1.0 or in my case: pi.0 🥧

Okay, I'm done unless someone points something out. 😀

Continued.

Is it 7 layers? From the photos you provided, I see:

red layer (top)
red layer (bottom)
blue
turquoise
pink
orange
green

6. there is only one red.

there are two 3d pics

Does anyone have any comment on what size capacitors should be used in the centre region? I noticed that AMD on their Opteron series use several dozen ceramic caps in the 50-470 nF range.

When I look at my Gainbery VRM module, I see a few of the larger caps in parallel, like 4x 47 uF, but on the bottom side, I see what looks like a dozen or more small ceramic caps, probably in the nanofarad range.

Should the centre region of this adaptor have caps in the 100-300 nF range or just more caps in the 10-100 uF range? If the centre region would have caps in the nanofarad range, then the footprint of 2312 is too large. I don't see any caps that fit 2312 in the 100-300 nF range. Smallest is 470 nF.

How far apart are the cap pads in the centre section? If the pads are large with a small gap between, then the smaller ceramic caps can fit.

EDIT:
Reading online about decoupling caps for ICs: seems that placing 10 nF in parallel with 100 nF and placing this combination next to each Vcc input pin is common. Some people just go with 10 nF, some 100 nF, some the parallel combination. However placing this combination next to each Vcc pin on the CPU would be a challenge. Thus I wonder if this combination should be placed in the centre section of the adaptor? If so, maybe the pads in here should be 1206 sizes?

Should be easy enough to install a slightly smaller cap on the larger footprint. Just watch the vias. Maybe put some kapton tape down.

If you have a good oscilloscope you could experiment. With different values

I’m a little rusty on this subject but I thought the lower the internal resistance and higher the capacitance, the better the filtering will be. So more lower resistance capacitors the better. But you can run into slow shutdown and high inrush issues if you go too big.

What's the [dielectric] gap between pads of the centre caps? This will let me know what size ceramic caps I can fit here.

Spacing

I wouldn't need the distatance between GND and GND on two different cap pads, but the distance from GND to VCC on the same cap. I think your second photo is showing this situation? If so, then the distance, or gap, between pads on a single capacitor section, is 2.845 mm? I'm not sure if any ceramic caps will span that distance, while also meeting the pad's width requirement.

2nd yes. 2.845.

Here is what you do,

Put down kapton tape.

Put down the cap where you want, and hold it somehow, like with a paperclip bent into a clamp or something.

Then fill the pad with solder and bridge it over to the cap, then repeat on other side.

I think I'll look for some thru-hole caps in a package similar to that of conventional resistors.

Axial capacitors. That might work. 🤔

You are wanting smaller values than the tantalums come in? Is this the problem?