Reply 280 of 306, by kool kitty89
Well, that 495SX board requires 8kx8-bit TAG RAM for a single 128kB (4x 32kx8-bit) bank of cache and dual 8kx8-bit TAG chips for the full 256 kB (dual 128kB banks) configuration that's installed.
My board still has the 20 ns cache and tag chips installed. (I tried substituting some faster 32kx8-bit SRAMs for TAG, but this board didn't like that at all in spite of the mostly identical pinout: I also tried isolating the extra address pins which are NC and CS2 on normal 8kB chips, but this board must make use of CS2 as it then hung at the RAM test rather than during DOS booting)
I'm pretty sure some boards aren't fussy about 32k vs 8k SRAMs installed as cache, even if they don't need 8k ones. (and even back then, I'm pretty sure the dropping cost and large supply of 32kB density SRAMs would've made that an appealing option to simplify logistics at the user/shop end)
Anyway, I'm not sure what exactly is going on in my case of if I can enable write-through cache on this board, but things that really like fast access to DRAM seem to run better with the L2 disabled entirely. The 640x480 PC Player benchmark in particular likes that and is faster with no L2 than with 2-2-2-2 cache timing for the L2 and even slightly faster than 2-1-1-1 timing if I don't have auto-configuration set in the advanced-chipset options. (which seems to be the only way to enable page-mode burst reads, or I'm guessing that's where the speed comes from)
2-1-1-1 timing + auto-config manages to be a little faster with L2 than without for PC Player VESA mode.
For most DOS benchmarks, the cache has a lot more benefit or at least not a disadvantage and both Quake and Doom prefer L2 to just faster DRAM, though I haven't done runs of 640x480 Quake yet.
I also worked out the VLB wait state settings on the board and set it for the 33 MHz (or slower) 0 wait option, which sped things up a little and also seems to work at 40 MHz with the Trident 9400 and Diamond Stealth 24 and I also switched the Trident card's own waits to zero but noticed the DRAM timing jumper was set for 60/70 ns and it has 80 ns 256kx16-bit chips (1MB 32-bit) soldered to the board, so I set that to 80 and cured the video artifacting problem it had had in SVGA/VESA resolutions. (looks like someone had previously set it up for 70 ns DRAM timing + waits for 40/50 MHz bus speed)
That Trident card is too bad like that now and both it and the S3 card seem to have cleaner video outputs than the Avance Logic one (there's a jailbar moire pattern on the Avance card that I thought was just scaling artifacts on my LCD VGA monitor, but those artifacts are almost absent on the Trident and totally on the Diamond card, plus seem absent in the Avance Logic card when using unchained 320x240 modes ... or maybe it's related to signal quality when running in 60 vs 70 Hz: since Doom runs in unchained mode and has the same artifacts as 13H/MCGA mode... and I haven't tried setting up a custom batch file in any of my games or benchmarks to adjust the VGA synch rates, though that's supposed to be possible for both vsynch and hsynch: ie allowing 15.7 kHz 60 Hz output too)
The Avance Logic card also seems to make the system unstable when 2-1-1-1 cache timing is enabled, but the other cards (and ISA cards) don't seem to do that.
I don't have a Tseng 4000 VLB card to directly compare, but I think the Avance Logic card might be closer to that speed range, though I think the Stealth 24 is supposed to be reasonably fast too (and better than the Mach 32 for example).
It's possible the Opti chipset is also bottlenecking these cards and the vogons wiki also mentions the 495SX added buffering to the VESA bus to improve stability (or compatibility) at the expense of performance, but I'm not sure that's true on the whole or simply referring to the board/chipset level wait state functionality.
I've also seen some reference to 'slow' ISA implementations on PCI 486 (and presumably Pentium/later) boards vs 'fast' ISA, but I'm not sure that's related to the behavior I noticed when comparing ISA video cards in Socket 7 boards vs ISA/VESA in that OPTI board.
I wish I could remember where I came across the slow ISA description but forgot to make a note of it. I think it came up when I was looking for documentation on some SiS 496/497 chipset based boards.
(I think it was the PCI400 and Zida Tomato 4DPS, which also seem to be virtually identical boards ... or actually identical depending on the specific revision of each: some revisions seem to include discrete keyboard controllers for example and others seem to lack them and have a bunch of resistors and capacitors in the spot where the keyboard chip was ... or would be: it actually seems like it's later revisions of boards that add the keyboard controller so maybe they had issues with the chipset integrated MCU)
Anyway, I'll need to double check my notes and screenshots, but I think 4.9 was the best score I got at 120 MHz with the Avance Logic card and L2 disabled. And I believe it dropped to 4.5 or 4.6 FPS with the cache enabled (in 2-2-2-2 timing)
And at 33 MHz fsb (100 MHz) with both the S3 and Trident cards I got 3.9 with the L2 cache off, 4.1 with cache (both with auto-config enabled), and 3.8 with auto-config disabled and 2-1-1-1 cache timing selected.
For some reason, the S3 card managed faster 3Dbench scores than the trident one, but not in PC Player, even at 320x200. (though as mentioned earlier, at 320x200 the L2 cache was already preferred enabled even with worst case)
Hmm, I also don't think there's a way to increase DRAM wait states and have page-mode burst cycles enabled. I could try messing with it more, but I think the BIOS ignores all the user input parameters for RAM/cache timing and maybe the ISA divider setting too when auto is enabled. (otherwise it would be easier to confirm that page mode is being used: turning up wait states and trying to enable/disable page-mode would show a much more dramatic bandwidth difference than minimal wait states, and burst read cycles would probably be 6-2-2-2 with 'zero' waits and 9-2-2-2 with 3 wait states)
I'm not sure why they bothed including that auto-config function and not user configurable DRAM timing and page mode enable/disable.
(also allowing 2 or 3 clock page mode cycle times would be useful for a wider array of DRAM speeds, but I'd assume a cheaper approach would just be to lock that at 2-tick timing and disable page-mode entirely for fast FSB + slow DRAM combinations, though I suppose locking it at 3 ticks would be a more conservative, cheap approach: also other considerations like if the DRAM controller runs at the bus clock or a fraction/multiple of it and/or if it's single-phase vs poly-phase clocked logic)
That Mustang SiS Socket 7 board does have fairly detailed EDO and FPM DRAM timing options in the BIOS, though that can be confusing in itself.