First post, by feipoa
- Rank
- l33t++
I am tyring to get this system setup, with an AMD X5-160 ADZ at 40x4.
At 40 MHz FSB, setting the cache write cycle to 2 and DRAM Speed to Fastest gives really nice cachechk speeds:
L1 Read: 165 MB/s
L2 Read: 75 MB/s
RAM Read: 51.5 MB/s
RAM Write: 83.6 MB/s
However the system is not stable in Windows. I need to set the cache write cycle up to 3 for the system to be stable enough in Windows to run the Quake 2 benchmark, or play mp3's continually.
Setting cache write cycle to 3 greatly lowers the Cachechk speeds as follows:
L1 Read: 165 MB/s
L2 Read: 75 MB/s
RAM Read: 39.4 MB/s
RAM Write: 55.7 MB/s
Strangely enough, it doesn't alter the L1/L2 cache speeds at all, only the RAM speed, which is what puzzles me. In checking the various DRAM Speed options of Normal, Fast, Faster, and Fastest, nothing above Fast increase the DRAM speed when cache write cycle is set to 3. I can also run the system with cache write cycle set to 2, however I cannot go above DRAM Speed: Faster. 2 with Faster gives the same memory throughput as 3 with fast/faster/fastest. 2 with Fastest gives the 51.5 MB/s again, but not stable enough in Wndows, even with 5 V going to the CPU.
I first thought that the Cache Write Cycle was the first character in the typical 2-1-2 or 2-1-1-1 which you may be used to. On other motherboards, going from 2-1-2 to 3-1-2 does not change the memory throughput. However, the BIOS Companion mentions that the Cache Write Cycle: Affects the data hold time for writes to DRAM.
Can anyone else with a Zida Tomato 4DPS motherboard see if the maximum cachechk memory read speed is 39.4 MB/s when the cache is set to 3-1-2 and everything else in the BIOS's chipset settings are optimised? I am thinking I must have pooched something on this board. Much appreciated!
Here are all the chipset settings for this motherboard,
ISA Bus Clock: 7.159 MHz, 1/3, or 1/4 of PCI Clock
LBD# Sample Point: End of T3 or End of T2
Cache Write Cycle: 2 CCLK or 3 CCLK
Cache Burst Read Cycle: 1 CCLK or 2 CCLK
L2 Cache / DRAM Cycle WS: 2 CCLK or ?
DRAM RAS to CAS Delay: 2 CCLK or 3 CCLK
DRAM Write Cycle: 0 WS or 1 WS
DRAM Write CAS Paline: 2 CCLK or ?
DRAM CAS Precharge Time: 1 CCLK or?
DRAM RAS to MA Delay: 1 CCLK or 2 CCLK
DRAM Speed: Normal, Fast, Faster, Fastest
DRAM Slow Refresh: Enabled or Disabled
L2 Cache Policy: Write Back or Write Through
L2 Cache Tag Bits: 7 bits or 8 bits
Plan your life wisely, you'll be dead before you know it.
