dnewhous wrote:I think you need to make a distinction between the CPU speed and the FSB (front side bus) speed. […]
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FGB wrote:"The usual story is..." - Well, what if "the story" isn't true? Read the VESA specs and tell the story again!
I think you need to make a distinction between the CPU speed and the FSB (front side bus) speed.
The glitch is mentioned on the wikipedia,
As bus speeds of 486 systems increased, VLB stability became increasingly difficult to manage. The tightly coupled local bus design that gave VLB its speed became increasingly intolerant of timing variations - notably past 40 MHz. Intel's original 50 MHz 486 processor faced difficulty in the market as many existing motherboards (even non-VLB designs) did not cope well with the increase in front side bus speed to 50 MHz. If one could achieve reliable operation of VLB at 50 MHz it was extremely fast – but again, this was notoriously difficult to achieve, and often it was discovered not to be possible with a given hardware configuration.[3]
The 486DX-50's successor, the 486DX2-66, circumvented this problem by using a slower but more compatible bus speed (33 MHz) and a multiplier (×2) to derive the processor clock speed.
https://en.wikipedia.org/wiki/VESA_Local_Bus
The article states that the VLB was P5 compatible, not P6, so if you fixed the timing glitch the best CPU would be
Tillamook 0.25 µm 166–300 MHz 32 KB 66 MHz Socket 7 August 1997
Umm, did you read my posting(s)? Maybe you were busy creating ten new threads while reading my answer to you 🤣 , but I was referring to the FSB speed of the CPU in my posting. The internal clock speed is not relevant for the VLB. For a bus the bus speed matters.
Wikipedia doesn't say otherwise as I posted before. And just because Wikipedia says it was "notoriously difficult to achieve" the 50MHz bus speed doesn't make it impossible or unlikely or a rare occurance. Wikipedia is one great source to learn things. But only one source out of many. Wikipedia isn't a fact book.
So again: VLB was specified for 40MHz bus speed maximum. That doesn't imply that more bus speed would "break" the bus as you told the "usual" story. It just becomes harder to achieve as therefore wasn't recommended for the casual user because several different parameters came into play such as cache timings, memory waitstates, clock dividers and the fact that having one card working at 50MHz FSB was only the beginning. The really hard part was to find a mathing controller card for the graphics card.
Regarding VLB implementations on other than the 486 platform:
I also wrote about this. Seems you missed it, too.
dnewhous wrote:The article states that the VLB was P5 compatible, not P6, so if you fixed the timing glitch the best CPU would be
Tillamook 0.25 µm 166–300 MHz 32 KB 66 MHz Socket 7 August 1997
The Tillamook is not a native desktop processor and can't be used on any VLB board without several hardware mods. It is possible, yes, but only as a demonstration of feasability. It was no upgrade path at all back in the day.
"VLB is P5 compatible" doesn't mean any P5 CPU is VLB compatible. P5 is a processor architecture while VLB is a bus implementation on the motherboard. There are no Socket 7 (P5) motherboards with the VLB - the last Socket with VLB was Socket 5 (also P5). These boards support 3.xVolt single voltage CPUs only. So no Socket 7 CPUs, no split volage CPUs (iMMX, K6-2, ...).
Of course one can use a Socket 5 board with a voltage adaptor, but that's another story.
Featurewise the IDT Winchip may be the latest CPU that may work in those Socket 5 boards with VLB bus, but in the real world it was like this back in the day:
1. Socket 4 VLB: Pentium 60 (most), Pentium 66 (few), Pentium 133 Overdrive (very few)
2. Socket 5 VLB: Pentium 75 (most), Pentium 90 (common), Pentium 100 (common)
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