I can't get L2 cache work in this motherboard with a am5x86 CPU and I have no clue why is that, L2 works perfectly fine with am486DX4. I have compared both of these CPUs pinouts and according to the datasheets - both are identical in pinout 😕 Has anyone dealt with this problem before?
I actually have the exact same problem right now. Did you happen to find any clue about this issue?
the motherboard may require a bios update, remember that the "L2" cache on 486 motherboards is on the motherboard, the processor has nothing to do here
DT: R7-5800X3D/R5-3600/R3-1200/P-G5400/FX-6100/i3-3225/P-8400/D-900/K6-2_550
LT: C-N2840/A64-TK57/N2600/N455/N270/C-ULV353/PM-1.7/P4-2.6/P133
TC: Esther-1000/Esther-400/Vortex86-366
Others: Drean C64c/Czerweny Spectrum 48k/Talent MSX DPC200/M512K/MP475
most likely the bios, I have a vlb board with a umc chipset and eveything works with L2 except a 5x86
wrote:I actually have the exact same problem right now. Did you happen to find any clue about this issue?
Not yet, I had to postpone researth on this matter. This motherboard uses a UMC UM82C482/UM82C481/UM82C206F chipset. I believe L2 not being detected issue is more chipset related than BIOS. I have another MB with exact same chipset, I'll test it too, some time later.
mine is UC4914-G using a um82c491f it detects l2 on a overdrive dx4 100 but not amd 5x86 133 they both have 16k L1 so I don't think its a larger L1 size the problem
Hi I have also run into this problem with a VL486 motherboard with UMC chipset (Stason https://stason.org/TULARC/pc/motherboards/U/U … -486-VL486.html).
Am5x86 133 won't recognise L2 cache. FYI Pentium Overdrive 83Mhz also does not recognise L2 cache (but these are known to have cache comapitibility problems). I have set cache jumpers for 64k, 128k and 256k and it made no difference. Cache chips are Winbond 15ns x 8 and one 10ns (TAG). DX-33, DX2-66 and DX2-80 detect the L2.
BIOS is "IPEX ITG IPX-UM-486IV6201 04/08/1993"
AMI BIOS string "40-0100-001131-00101111-111192-UMC480-H"
I have an EPROM reader and UV eraser. I can provide a copy of the AMI BIOS if this can be modified by someone more intelligent than me?
Thanks all, look forward to your suggestions.
SSTV2 wrote on 2019-08-05, 22:12:wrote:I actually have the exact same problem right now. Did you happen to find any clue about this issue?
Not yet, I had to postpone researth on this matter. This motherboard uses a UMC UM82C482/UM82C481/UM82C206F chipset. I believe L2 not being detected issue is more chipset related than BIOS. I have another MB with exact same chipset, I'll test it too, some time later.
Hi SSTV2, did you get a chance to test with your other motherboard with same chipset? If yes, what was the outcome?
I did some further testing and I reduced the bus speed to 20mhz and ran the processor at 80mhz and 60mhz. But still the L2 cache won't detect.
Hi,
both motherboards were tested thoroughly (UM486V and GA-486VM), but neither could detect L2 cache with a 5x86 CPU inserted. I had tried all possible BIOS settings and jumper configurations, related to L2 cache, but nothing could make it work, even tried various BIOS images from chipset-compatible motherboards, including one MRBIOS image - no go. I think this issue is related to the outdated chipset (in relation to 5x86), the UM82C480 was introduced in 1991 for 386/early 486 CPUs, so some incompatibilty can be expected with its cache controller. By the way, this chipset doesn't support WB cache mode, better stick with a PCI supporting chipset, if you wish to max out the performance of a 5x86.
Sorry for the delayed reply, after the forum UI update, I rarely browse here.
Many thanks for your assistance SSTV2. I managed to get my Am5x86 running at 150mhz using 3 x 50mhz. So this somewhat compensates for the lack of L2. It is definitely faster than an dx2-80 with 256kb l2 enabled. Now just need a VLB IDE card capable of running at 50MHz for some extra performance.
I managed to get my Am5x86 running at 150mhz using 3 x 50mhz. So this somewhat compensates for the lack of L2
Am5x86 150-160Mhz without L2 cache is more or less equal to 120Mhz 486DX4 with L2 cache.
I must be some kind of standard: the anonymous gangbanger of the 21st century.
After the am5x86 CPU upgrade in the PCI 486 system with a more stable one, I had the old one lying around unused for a while, so I decided to take another look at the am5x86 and UM82C480 chipset incompatibility problem with the L2 cache.
My previous assumption, that the chipset is the main cause of this incompatibility - is wrong, it's indeed the outdated BIOS that does not enable L2 cache with the said CPU, intel DX4 ODPR and P24T (as seen here @pshipkov) are also affected. I found three different AMI BIOS versions for this ECS UM486V motherboard and all of them are built on 11/11/92 core, latest one being ver. 2.2 with the date code of 11/19/93, unfortunately, it's no different than the previous two versions regarding the L2 cache detection.
I tried tricking the BIOS into seeing all 486 CPUs as 486 DX2 in the POST summary screen, by changing one mask byte from B3 to B6 (found @32Dh of all the ECS 11/11/92 core versions) in the CPU detection routine, but that didn't help, routine's task seems to be just visual. Level 2 cache is enabled/disabled long before the POST summary screen appears.
Eventually I stopped experimenting with the original BIOS because I didn't know exactly what to look for and it didn't help that I had to rewrite the BIOS every time I made changes. Emulators didn't help here either, because they don't properly emulate the cache operation.
Now for the good news. The UM82C480 chipset can indeed work with an am5x86 and L2 cache enabled, I was able to find two BIOS images that properly detected L2 cache, one was from MRBIOS, the other from Phoenix. The previous MRBIOS image I tried was version 1.44 and the new one is version 1.65.
Speedsys results, am5x86 @ 163MHz in 3x mode:
Here are some more interesting snippets of the disassembled AMI BIOS, in case anyone decides to find out exactly why the L2 cache doesn't work with the newer CPUs. Disassembled by IDA 6.1, AMI BIOS of GA-486VM, core 11/11/92.
CPU type detection routine:F000:442C ; =============== S U B R O U T I N E =======================================F000:442CF000:442CF000:442C sub_F442C proc near ; CODE XREF: sub_F4265+Cp CHECK IF 286 CLASS CPUF000:442C pushfF000:442D cliF000:442E mov ax, 0F000hF000:4431 push axF000:4432 popfF000:4433 pushfF000:4434 pop axF000:4435 and ah, 0F0hF000:4438 mov si, 475EhF000:443B jz short loc_F449E ;CALL sub_F4248 STRING DISPLAYF000:443D smsw axF000:4440 or ah, ahF000:4442 jz short loc_F4474F000:4444F000:4444 loc_F4444: ; CODE XREF: sub_F442C+4Fj CHECK IF 386 CLASS CPUF000:4444 push axF000:4445 mov eax, cr0F000:4448 push eaxF000:444A and al, 0EFhF000:444C mov cr0, eaxF000:444F mov eax, cr0F000:4452 test al, 10hF000:4454 pop eaxF000:4456 mov cr0, eaxF000:4459 pop axF000:445A mov si, 473EhF000:445D jnz short loc_F4468F000:445F or ah, ahF000:4461 jnz short loc_F449C ;MOV AH FFH, THEN CALL sub_F4248 STRING DISPLAYF000:4463 mov si, 477EhF000:4466 jmp short loc_F449C ;MOV AH FFH, THEN CALL sub_F4248 STRING DISPLAYF000:4468 ; ---------------------------------------------------------------------------F000:4468F000:4468 loc_F4468: ; CODE XREF: sub_F442C+31jF000:4468 mov si, 474EhF000:446B or ah, ahF000:446D jnz short loc_F449C ;MOV FF TO AH, THEN CALL sub_F4248 STRING DISPLAYF000:446F mov si, 476EhF000:4472 jmp short loc_F449C ;MOV FF TO AH, THEN CALL sub_F4248 STRING DISPLAYF000:4474 ; ---------------------------------------------------------------------------F000:4474F000:4474 loc_F4474: ; CODE XREF: sub_F442C+16j CHECK IF 486 CLASS CPUF000:4474 mov al, 0B3h ; '¦'F000:4476 call sub_FEE94F000:4479 test al, 4 ; B3 AND 4 = 0F000:447B jnz short loc_F4444 ; IF NOT 0, MUST BE A 386F000:447D test al, 2 ; B3 AND 2 = 2F000:447F mov si, 470Eh ; "80486DX2" STRINGF000:4482 jnz short loc_F449C ;MOV FF TO AH, THEN CALL sub_F4248 STRING DISPLAYF000:4484 int 11h ; EQUIPMENT DETERMINATIONF000:4484 ; Return: AX = equipment flag bitsF000:4486 test al, 2F000:4488 mov si, 471Eh ; "486DX or 487SX" STRINGF000:448B jnz short loc_F449C ;MOV FF TO AH, THEN CALL sub_F4248 STRING DISPLAY
F000:448D mov al, cs:byte_FB5B5F000:4491 call sub_F8300F000:4494 mov si, 46FEh ; "80486" STRINGF000:4497 jz short loc_F449C ;MOV FF TO AH, THEN CALL sub_F4248 STRING DISPLAYF000:4499 mov si, 472Eh ; "80486SX" STRINGF000:449CF000:449C loc_F449C: ; CODE XREF: sub_F442C+35jF000:449C ; sub_F442C+3Aj ...F000:449C mov ah, 0FFhF000:449EF000:449E loc_F449E: ; CODE XREF: sub_F442C+FjF000:449E call sub_F4248F000:44A1 popfF000:44A2 retnF000:44A2 sub_F442C endpStrings at the summary screen:F000:19B0 db 10hF000:19B1 db 14hF000:19B2 db 19hF000:19B3 db 21h ; !F000:19B4 db 28h ; (F000:19B5 db 32h ; 2F000:19B6 db 42h ; BF000:19B7 db 50h ; PF000:19B8 db 4Dh ; MF000:19B9 db 48h ; HF000:19BA db 7Ah ; zF000:19BB db 20hF000:19BC db 43h ; CF000:19BD db 50h ; PF000:19BE db 55h ; UF000:19BF db 20hF000:19C0 db 43h ; CF000:19C1 db 6Ch ; lF000:19C2 db 6Fh ; oF000:19C3 db 63h ; cF000:19C4 db 6Bh ; kF000:19C5 db 0DhF000:19C6 db 0AhF000:19C7 db 0F000:19C8 db 4Dh ; MF000:19C9 db 48h ; HF000:19CA db 7Ah ; zF000:19CB db 20hF000:19CC db 44h ; DF000:19CD db 58h ; XF000:19CE db 32h ; 2F000:19CF db 20hF000:19D0 db 43h ; CF000:19D1 db 50h ; PF000:19D2 db 55h ; UF000:19D3 db 20hF000:19D4 db 0DhF000:19D5 db 0AhF000:19D6 db 0F000:19D7 db 4Bh ; KF000:19D8 db 42h ; BF000:19D9 db 20hF000:19DA db 43h ; CF000:19DB db 41h ; AF000:19DC db 43h ; CF000:19DD db 48h ; HF000:19DE db 45h ; EF000:19DF db 20hF000:19E0 db 4Dh ; MF000:19E1 db 45h ; EF000:19E2 db 4Dh ; MF000:19E3 db 4Fh ; OF000:19E4 db 52h ; RF000:19E5 db 59h ; YF000:19E6 db 0DhF000:19E7 db 0AhF000:19E8 db 0F000:19E9 db 0F000:19EA db 0F000:19EB db 4F000:19EC db 10hF000:19ED db 0F000:19EE db 2F000:19EF db 18hF000:19F0 db 0F000:19F1 db 1F000:19F2 db 1ChF000:19F3 db 80h ; ÇF000:19F4 db 0F000:19F5 db 1EhF000:19F6 db 40h ; @F000:19F7 db 0F000:19F8 db 1FhF000:19F9 db 20hF000:19FA db 0F000:19FB db 0FFhF000:19FCF000:19FC ; =============== S U B R O U T I N E =======================================F000:19FCF000:19FCF000:19FC sub_F19FC proc near ; CODE XREF: sub_F4234+9pF000:19FC mov ax, cs:word_F82E6F000:1A00 call axF000:1A02 mov al, 92h ; 'Æ'F000:1A04 call sub_F8DBAF000:1A07 test al, 1F000:1A09 jz short loc_F1A2CF000:1A0B mov al, 93h ; 'ô'F000:1A0D call sub_F8DBAF000:1A10 and al, 1FhF000:1A12 mov bl, alF000:1A14 mov si, 19E9hF000:1A17F000:1A17 loc_F1A17: ; CODE XREF: sub_F19FC+25jF000:1A17 lods byte ptr cs:[si]F000:1A19 cmp al, 0FFhF000:1A1B jz short loc_F1A7FF000:1A1D cmp al, blF000:1A1F lods word ptr cs:[si]F000:1A21 jnz short loc_F1A17F000:1A23 call loc_F09FDF000:1A26 mov si, 19D7hF000:1A29 call sub_FF52EF000:1A2CF000:1A2C loc_F1A2C: ; CODE XREF: sub_F19FC+DjF000:1A2C ; sub_F19FC+86jF000:1A2C call sub_F2C27F000:1A2F jz short locret_F1A7EF000:1A31 mov ax, 0B3B3hF000:1A34 call sub_FEE94F000:1A37 test al, 2F000:1A39 jz short loc_F1A5EF000:1A3B mov ax, 0B3B3hF000:1A3E call sub_FEE94F000:1A41 and al, 70hF000:1A43 shr al, 4F000:1A46 xor ah, ahF000:1A48 mov si, 19B0hF000:1A4B add si, axF000:1A4D mov al, cs:[si]F000:1A50 xor ah, ahF000:1A52 call loc_F09FDF000:1A55 mov si, 19C8hF000:1A58 call sub_FF52EF000:1A5B jmp short locret_F1A7EF000:1A5B ; ---------------------------------------------------------------------------F000:1A5D db 90h ; ÉF000:1A5E ; ---------------------------------------------------------------------------F000:1A5EF000:1A5E loc_F1A5E: ; CODE XREF: sub_F19FC+3DjF000:1A5E mov ax, 0B3B3hF000:1A61 call sub_FEE94F000:1A64 and al, 70hF000:1A66 shr al, 4F000:1A69 xor ah, ahF000:1A6B mov si, 19B0hF000:1A6E add si, axF000:1A70 mov al, cs:[si]F000:1A73 xor ah, ahF000:1A75 call loc_F09FDF000:1A78 mov si, 19B8hF000:1A7B call sub_FF52EF000:1A7EF000:1A7E locret_F1A7E: ; CODE XREF: sub_F19FC+33jF000:1A7E ; sub_F19FC+5FjF000:1A7E retnF000:1A7F ; ---------------------------------------------------------------------------F000:1A7FF000:1A7F loc_F1A7F: ; CODE XREF: sub_F19FC+1FjF000:1A7F call sub_F8D72F000:1A82 jmp short loc_F1A2CF000:1A82 sub_F19FC endpCache (internal?) enabling/disabling:F000:8C42 loc_F8C42: ; CODE XREF: sub_F8B87+B5jF000:8C42 mov eax, cr0F000:8C45 and eax, 9FFFFFFFhF000:8C4B mov cr0, eaxF000:8C4E cliF000:8C4F mov eax, cr0F000:8C52 or eax, 40000000hF000:8C58 mov cr0, eaxF000:8C5B mov ax, 14C0hF000:8C5E out 22h, alF000:8C60 jcxz short $+2F000:8C62 jcxz short $+2F000:8C64 xchg ah, alF000:8C66 out 23h, alF000:8C68 jcxz short $+2F000:8C6A jcxz short $+2F000:8C6C mov ax, 0AC5hF000:8C6F out 22h, alF000:8C71 jcxz short $+2F000:8C73 jcxz short $+2F000:8C75 xchg ah, alF000:8C77 out 23h, alF000:8C79 jcxz short $+2F000:8C7B jcxz short $+2F000:8C7D mov ax, 6C6hF000:8C80 out 22h, alF000:8C82 jcxz short $+2F000:8C84 jcxz short $+2F000:8C86 xchg ah, alF000:8C88 out 23h, alF000:8C8A jcxz short $+2F000:8C8C jcxz short $+2F000:8C8E mov ax, 0CC8hF000:8C91 out 22h, alF000:8C93 jcxz short $+2F000:8C95 jcxz short $+2F000:8C97 xchg ah, alF000:8C99 out 23h, alF000:8C9B jcxz short $+2F000:8C9D jcxz short $+2F000:8C9F mov ax, 7C9hF000:8CA2 out 22h, alF000:8CA4 jcxz short $+2F000:8CA6 jcxz short $+2F000:8CA8 xchg ah, alF000:8CAA out 23h, alF000:8CAC jcxz short $+2F000:8CAE jcxz short $+2F000:8CB0 mov ax, 0CBh ; '-'F000:8CB3 out 22h, alF000:8CB5 jcxz short $+2F000:8CB7 jcxz short $+2F000:8CB9 xchg ah, alF000:8CBB out 23h, alF000:8CBD jcxz short $+2F000:8CBF jcxz short $+2F000:8CC1 mov ax, 0CCh ; '¦'F000:8CC4 out 22h, alF000:8CC6 jcxz short $+2F000:8CC8 jcxz short $+2F000:8CCA xchg ah, alF000:8CCC out 23h, alF000:8CCE mov ax, 0CEh ; '+'F000:8CD1 out 22h, alF000:8CD3 jcxz short $+2F000:8CD5 jcxz short $+2F000:8CD7 xchg ah, alF000:8CD9 out 23h, alF000:8CDB jcxz short $+2F000:8CDD jcxz short $+2F000:8CDF mov ax, 0CFh ; '-'F000:8CE2 out 22h, alF000:8CE4 jcxz short $+2F000:8CE6 jcxz short $+2F000:8CE8 xchg ah, alF000:8CEA out 23h, alF000:8CEC mov eax, cr0F000:8CEF and eax, 9FFFFFFFhF000:8CF5 mov cr0, eaxF000:8CF8F000:8CF8 loc_F8CF8: ; CODE XREF: sub_F8B87:loc_F8C3FjF000:8CF8 jmp diF000:8CF8 sub_F8B87 endp
Older MRBIOS:
Can it be enabled after boot using software?
Perhaps CHKCPU has thoughts on this.
Be sure to upload afflicted and working bioses so people can play with them.
