majestyk wrote on 2023-03-03, 14:42:

GigAHerZ wrote on 2023-03-02, 20:39:

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Question about the speedsys' graph - shouldn't we see the blue line (write speed) also represent difference between L1 and L2 cache "space" when write-back is enabled?

Wow - are you running 50 MHz FSB with a VLB video card? If so, which one is it?

Isn´t the higher throughput for memory writes rather a matter of "Write Policy" / Write Allocation" than "Write Policy" /Write Back? Early Intel and AMD CPUS lacked some of the features.

It's a Trio32 VLB variant. It also is fine with Trio64 BIOS, which performs a bit better. (based on speedsys' video ram speed)
It's a speedy demon. 😀 But if there's a chance to push it even more, i want to make it happen.

Mine runs fine @ 40 MHz, 8MHz AT-bus and fast memory timings.

GigAHerZ wrote on 2023-03-02, 20:39:

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Question about the speedsys' graph - shouldn't we see the blue line (write speed) also represent difference between L1 and L2 cache "space" when write-back is enabled?

It seems like SpeedSys uses a cold cache before writing data. A 486 system won't benefit in this situation.

Disruptor wrote on 2023-03-03, 22:23:

GigAHerZ wrote on 2023-03-02, 20:39:

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Question about the speedsys' graph - shouldn't we see the blue line (write speed) also represent difference between L1 and L2 cache "space" when write-back is enabled?

It seems like SpeedSys uses a cold cache before writing data. A 486 system won't benefit in this situation.

Exactly, I wrote a detailed explanation at Re: Pentium MMX 450MHz some time ago.

majestyk wrote on 2023-03-03, 14:42:

GigAHerZ wrote on 2023-03-02, 20:39:

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Wow - are you running 50 MHz FSB with a VLB video card? If so, which one is it?

pre VLB, or at the very start some companies shipped factory 50MHz systems: Re: Pre-VESA Proprietary 32-bit Local Buses?
> Swan 486/50 DB running S3 86c924 at 50MHz

interestingly both S3 86C911 and 86C924 are supposed to be ISA designs, would love to see the insides of a 'Swan 486/50 DB'

rasz_pl wrote on 2023-03-04, 09:19:

interestingly both S3 86C911 and 86C924 are supposed to be ISA designs, would love to see the insides of a 'Swan 486/50 DB'

The 86C911 is not an ISA-only chip. It is intended to be connectable to a 32-bit local bus as well. While I was unable to find a PDF data sheet for S3 chips older than the 928, US patent 5426739 describing the Opti Local Bus shows a local-bus connected 86c911 as an application example on page 17 ("figure 19").

mkarcher wrote on 2023-03-04, 09:52:

rasz_pl wrote on 2023-03-04, 09:19:

interestingly both S3 86C911 and 86C924 are supposed to be ISA designs, would love to see the insides of a 'Swan 486/50 DB'

The 86C911 is not an ISA-only chip. It is intended to be connectable to a 32-bit local bus as well. While I was unable to find a PDF data sheet for S3 chips older than the 928, US patent 5426739 describing the Opti Local Bus shows a local-bus connected 86c911 as an application example on page 17 ("figure 19").

I was going off vgamuseum.info
http://www.vgamuseum.info/index.php/news/item/952-s3-p86c924
http://www.vgamuseum.info/index.php/news/item/342-s3-p86c911
but yes, clearly they have to be local bus capable if SWAN ran them at 50MHz

mkarcher wrote on 2023-03-03, 22:29:

Disruptor wrote on 2023-03-03, 22:23:

GigAHerZ wrote on 2023-03-02, 20:39:

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Question about the speedsys' graph - shouldn't we see the blue line (write speed) also represent difference between L1 and L2 cache "space" when write-back is enabled?

It seems like SpeedSys uses a cold cache before writing data. A 486 system won't benefit in this situation.

Exactly, I wrote a detailed explanation at Re: Pentium MMX 450MHz some time ago.

Thank you! That explains it well.

Any good tool that would reliably test if the L1 (and why not also L2) cache actually works properly in write-back mode? Any good experience with some tool?

GigAHerZ wrote on 2023-03-04, 12:55:

Any good tool that would reliably test if the L1 (and why not also L2) cache actually works properly in write-back mode? Any good experience with some tool?

You could use Heise's "ctcm" utitility (c't Cache Measurement), made by the german IT magazine "c't". An official download link is ftp://ftp.heise.de/pub/ct/ctsi/ctcm17a.zip , on a 486 computer that version should be invoked with "/NOP" to prevent a crash. In most cases, this utility can correctly identify the cache mode, and whether a write-back L2 cache runs in "always dirty" mode or in a proper configuration.

That´s the latest version 1.7 that is perfect for most later systems like socket 5 and 7.
For older 386/486 systems I prefer the old "1.0" version:

It doesn´t crash and outputs all the information you need.

Here´s the report for my FIC 486-PVT-IO

It reported "Dirty TAG L2: N/A" before I enabled "Combine Alter & TAG Bits" in BIOS.

majestyk wrote on 2023-03-04, 18:20:

For older 386/486 systems I prefer the old "1.0" version:

Thanks for attaching that version, although the screenshot clearly shows it's version 1.5b, not version 1.0. Nevertheless, it's a good version to run on a 486 system, and your screenshot is a good reference for the output of ctcm on a properly configured Am5x86 L1WB/L2WB system. "Dirty TAG L2: N/A" would indicate L2WB in "always dirty" mode, which is slower than L2 write-through in many use cases.

mkarcher wrote on 2023-03-04, 18:14:

GigAHerZ wrote on 2023-03-04, 12:55:

Any good tool that would reliably test if the L1 (and why not also L2) cache actually works properly in write-back mode? Any good experience with some tool?

You could use Heise's "ctcm" utitility (c't Cache Measurement), made by the german IT magazine "c't". An official download link is ftp://ftp.heise.de/pub/ct/ctsi/ctcm17a.zip , on a 486 computer that version should be invoked with "/NOP" to prevent a crash. In most cases, this utility can correctly identify the cache mode, and whether a write-back L2 cache runs in "always dirty" mode or in a proper configuration.

I've tried this, 1.5, 1.6 and 1.7 and it seems to show complete BS when you have 1024kB of L2 cache.
1.5 says there is no L2 cache.
1.6 and 1.7 say that there's 2048kB of cache and everything is in write-through mode. (Thanks for the /nop hint!)

But i've modified the bios ( QDI V4S471/G locks up with 1024kB of cache [Fixed! Nicer Award BIOS available!] ) and i'm absolutely sure that at least L2 cache is in write-back mode.

EDIT:
But thanks to this thread, i started tracing the tracks on the motherboard and this is the information about my QDI board. ( https://theretroweb.com/motherboards/s/qdi-v4s471-g )
JP44: Multiplier. 1-2=4x, 2-3=3x
JP18: DACK1. 1-2=Pull-down, 2-3=Pull-up
JP19: DACK0. 1-2=Pull-down, 2-3=Pull-up
J14: pull-down CPU B13 "WB/WT"
J11: pull-up CPU B13 "WB/WT"
J12-1: CPU B12 "Cache"
JP29-2: CPU A12 "HITM"
JP28-1 = pull-up
JP28-2 = CPU A10 "INV"
JP28-3 = CHIPSET 104 "W/R"
JP8-2: CHIPSET 118 "PCD"

This thread has a lot of good information. Thank you! I'm tracing that information all back to my board and hopefully i'm going to have a blazing fast 1MB L2 cache equipped 486. 😀

EDIT2: I think i got everything working now. The L1 cache speed jumped from ~89MB/s to ~129MB/s. Love it.
NB! The CTCM 1.6 and 1.7 claim that i have 2048kB of L2 cache and both L1 and L2 work in write-through mode. CTCM 1.5 doesn't recognize L2 cache at all, but at least claims that L1 is working in write-back mode.
Am i correct that L1 WB can be "detected" by seeing higher "copy" speed in speedsys than the "read" speed is? Is it always the case or am i "special"?

GigAHerZ wrote on 2023-03-04, 19:25:

EDIT2: I think i got everything working now. The L1 cache speed jumped from ~89MB/s to ~129MB/s. Love it.
NB! The CTCM 1.6 and 1.7 claim that i have 2048kB of L2 cache and both L1 and L2 work in write-through mode. CTCM 1.5 doesn't recognize L2 cache at all, but at least claims that L1 is working in write-back mode.
Am i correct that L1 WB can be "detected" by seeing higher "copy" speed in speedsys than the "read" speed is? Is it always the case or am i "special"?

How are you getting 170+ MB on your memory bandwidth test in SPEEDSYS? I get 76 MB/s on my Shuttle HOT-433... Can I see a screenshot of your BIOS memory settings please?

EDIT: nevermind, I found this thread...

GigAHerZ wrote on 2023-03-04, 19:25:

Am i correct that L1 WB can be "detected" by seeing higher "copy" speed in speedsys than the "read" speed is? Is it always the case or am i "special"?

Yes, that's a very good indicator of proper working L1WB cache. While the write test of speedsys misses L1/L2 all the time, the move test moves likely from one address to the same address, so it writes to those addresses that were just loaded for reading, so you get write hits all the time. If all writes are hits, and the whole amount of test memory fits L1, so nothing needs to be written back to L2 or main memory, you get the most of L1WB.

I just compared the speedsys benchmarks of the ABIT AB-AH4T with those of my Chaintech 486SPM (M102B) also running @ 160MHz at the fastest memory settings. The 486SPM has the follow up SIS chipset 85C496 / 497 with PCI support (and onboard super I/O) I also added PS2 mouse support.

I was surprised there´s virtually no significant difference between the two chipsets as far as memory performance is concerned.

GigAHerZ wrote on 2023-03-04, 19:25:

I've tried this, 1.5, 1.6 and 1.7 and it seems to show complete BS when you have 1024kB of L2 cache. 1.5 says there is no L2 cac […]
Show full quote

mkarcher wrote on 2023-03-04, 18:14:

GigAHerZ wrote on 2023-03-04, 12:55:

Any good tool that would reliably test if the L1 (and why not also L2) cache actually works properly in write-back mode? Any good experience with some tool?

You could use Heise's "ctcm" utitility (c't Cache Measurement), made by the german IT magazine "c't". An official download link is ftp://ftp.heise.de/pub/ct/ctsi/ctcm17a.zip , on a 486 computer that version should be invoked with "/NOP" to prevent a crash. In most cases, this utility can correctly identify the cache mode, and whether a write-back L2 cache runs in "always dirty" mode or in a proper configuration.

I've tried this, 1.5, 1.6 and 1.7 and it seems to show complete BS when you have 1024kB of L2 cache.
1.5 says there is no L2 cache.
1.6 and 1.7 say that there's 2048kB of cache and everything is in write-through mode. (Thanks for the /nop hint!)

But i've modified the bios ( QDI V4S471/G locks up with 1024kB of cache [Fixed! Nicer Award BIOS available!] ) and i'm absolutely sure that at least L2 cache is in write-back mode.

EDIT:
But thanks to this thread, i started tracing the tracks on the motherboard and this is the information about my QDI board. ( https://theretroweb.com/motherboards/s/qdi-v4s471-g )
JP44: Multiplier. 1-2=4x, 2-3=3x
JP18: DACK1. 1-2=Pull-down, 2-3=Pull-up
JP19: DACK0. 1-2=Pull-down, 2-3=Pull-up
J14: pull-down CPU B13 "WB/WT"
J11: pull-up CPU B13 "WB/WT"
J12-1: CPU B12 "Cache"
JP29-2: CPU A12 "HITM"
JP28-1 = pull-up
JP28-2 = CPU A10 "INV"
JP28-3 = CHIPSET 104 "W/R"
JP8-2: CHIPSET 118 "PCD"

This thread has a lot of good information. Thank you! I'm tracing that information all back to my board and hopefully i'm going to have a blazing fast 1MB L2 cache equipped 486. 😀

EDIT2: I think i got everything working now. The L1 cache speed jumped from ~89MB/s to ~129MB/s. Love it.
NB! The CTCM 1.6 and 1.7 claim that i have 2048kB of L2 cache and both L1 and L2 work in write-through mode. CTCM 1.5 doesn't recognize L2 cache at all, but at least claims that L1 is working in write-back mode.
Am i correct that L1 WB can be "detected" by seeing higher "copy" speed in speedsys than the "read" speed is? Is it always the case or am i "special"?

Hi,
When ctcm cannot detect the amount of l2 cache automatically, you can specify it.

for example
ctcm /l2=1024

majestyk wrote on 2023-03-10, 08:56:

I just compared the speedsys benchmarks of the ABIT AB-AH4T with those of my Chaintech 486SPM (M102B) also running @ 160MHz at t […]
Show full quote

I just compared the speedsys benchmarks of the ABIT AB-AH4T with those of my Chaintech 486SPM (M102B) also running @ 160MHz at the fastest memory settings. The 486SPM has the follow up SIS chipset 85C496 / 497 with PCI support (and onboard super I/O) I also added PS2 mouse support.
486SPM_102_B.JPG

486SPM_speeds.JPG

I was surprised there´s virtually no significant difference between the two chipsets as far as memory performance is concerned.

Are you sure, that you have fastest memory timings? cache through put is good (2-1-1-1 and 2 obviously), but......
I have ~10MB/s more on the Asus SV2GX4:

GigAHerZ wrote on 2023-03-04, 19:25:

.......
NB! The CTCM 1.6 and 1.7 claim that i have 2048kB of L2 cache and both L1 and L2 work in write-through mode. CTCM 1.5 doesn't recognize L2 cache at all, but at least claims that L1 is working in write-back mode.
Am i correct that L1 WB can be "detected" by seeing higher "copy" speed in speedsys than the "read" speed is? Is it always the case or am i "special"?

I think for 486 it is better to use ctcm1.5
But I confirm that 1MB L2 cache is not detected properly.
as already mentioned ctcm /l2=1024 does the trick.
Values seem to be OK, for me L1 WB and L2 WB with working dirty is shown correctly

Thank you! CTCM 1.5 with pre-defined L2 cache size works and confirms that my 486 is in top-notch configuration. (Y)

Setting "Cache TAG Bits" from 8 (default) to 7 makes the difference in memory throughput performance in my case. When I set it to 7 the speedsys benchmarks are very similar to thoseCoffee One has:

I´m not sure what the reason is here, do you need 8-bit for larger RAM sizes? I only tested 64M (4 x 16M).
These are my current chipset settings:

I also tried "DRAM RAS to CAS Delay" set to "2" but then the system hangs after memory count.

EDIT:
It´s always a good idea to have a look at the output of CTCM 1.7 also:

The cacheable area is limited to 32MB under the 7 bit cache tag setting. "Coffee One" has the higher memory throughput with 64M RAM - because he has populated 1M L2 cache! Probably you need 512K for 64M (and 1M for 128M RAM).
So if you run a mainboard with this chipset with 256K L2 cache make sure you use 32M RAM or less and find a way to set TAG bits to 7 - or upgrade L2 cache 😀

It´s always a lot of work to make benchmarks really comparable...