...cont´d...

The result´s don´t look bad:

I still would love to be able to turn WB on or off. Here´s the latest BIOS I used:

I also tried to edit the chipset register ("50", bit 4 and 3), but one of the bit´s cannot be edited as it seems.

Maybe someone here can throw it into modbin and have a guess what´s to be done...

majestyk wrote on 2023-02-27, 09:55:

After editing it with Modbin and enabling all the disabled entries under "chipset features" and rearranging the entries so all of them fit into the left and right table I found the entry "Internal Cache WB/WT" wouldn´t show up in the menue in the left table, a blank line is presented instead (you can also see this in the Modbin preview). Moving it to the right table didn´t help either.

That's not a bug, that's a feature: This setup option is ignored unless you install a Cyrix processor. While the cache mode on AMD and Intel processors is hardware controlled, the cache mode on Cyrix processors is BIOS controlled. Unlike many other BIOSes that always show this option, your BIOS is smart enough to hide the option in cases where it wouldn't have an effect anyway.

majestyk wrote on 2023-02-27, 09:55:

According to the AMD x586 datasheet this pin needs to be pulled up during reset to enable WB. I pulled it up with a resistor but either - when the resistor is >47K, WB is not enabled, or, when the reststor is about 10K (or less) the system crashes with a garbled screen at DOS-prompt.
When the pull-up resistor is present during POST and removed immediately after, then WB gets enabled correctly and the system works perfectly.

No, not really. When you do this, you do enable the L1WB protocol during reset, and thus you will recieve the "DX4 WB" or "5x86 WB" CPUID from the processor, but you will still operate in write-through mode. Everytime a cache line is loaded into the L1 cache, the processor samples the WB/WT pin, and if that pin is high, it allows write-back on that cache line. If that pin is is low, that cache line will operate in write-through mode. As you ground that pin after the reset, the processor runs in a mode that would support write-back, but every single cache line the processor caches is flagged as "no write-back on this cache line please".

It's not surprising that you need this to get stable operation. Write-back L1 cache needs mainboard support! In case of non-processor bus activity (PCI busmasters, ISA DMA), the chipset and processor need to cooperate to ensure cache coherence (this is called "cache snooping"). In write-through mode, cache snooping is only required on DMA writes, and happens just by telling the processor the address that got written to. In turn, the processor invalidates the contents of a line in the L1 cache, if it has that address cached. That's all. On the other hand, in write-back mode, the chipset needs to inform the processor about reads, too. If the processor happens to have new data for that address in the L1 cache that has not yet been written to L2 cache / main memory, the processor tells the chipset to hold back the DMA cycle and then goes on to write back the dirty L1 line to main memory. For this to happen, a more complex protocol is required. When you pull WB/WT high during reset, you promise the processor to support the more complex L1WB snooping protocol (in the Intel PODP/DX4-WB variation, not in the Cyrix variation). In case of the SiS471 chipset, the L1WB protocol is activated by a combination of jumpers to select the cache coherence protocol and a configuration bit to repsond to write back cycles. Furthermore, the L1WB protocol signals and INV and HITM need to be connected between the processor and the chipset. Your mainboard is too old to support the DX4-WB pinout, so you need to re-route some signals. http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm has a comprehensive overview on 486 pinouts. Your board supports the PODP, so it is able to interpret the signals sent by an 5x86, but it requires to receive them on pins on the outer row that is not present on the 5x86. Instead, the AMD 5x86 sends them on pins that the Cyrix 486 processors use for different purposes. Supporting L1WB thus means you have to disconnect the pins from their cyrix functions (cut traces) and re-wire them to the DX4-WB/5x86 functions, by connecting them to the corresponding PODP pins.

mkarcher wrote on 2023-02-27, 18:41:

It's not surprising that you need this to get stable operation. Write-back L1 cache needs mainboard support! In case of non-processor bus activity (PCI busmasters, ISA DMA), the chipset and processor need to cooperate to ensure cache coherence (this is called "cache snooping"). In write-through mode, cache snooping is only required on DMA writes, and happens just by telling the processor the address that got written to. In turn, the processor invalidates the contents of a line in the L1 cache, if it has that address cached. That's all. On the other hand, in write-back mode, the chipset needs to inform the processor about reads, too. If the processor happens to have new data for that address in the L1 cache that has not yet been written to L2 cache / main memory, the processor tells the chipset to hold back the DMA cycle and then goes on to write back the dirty L1 line to main memory. For this to happen, a more complex protocol is required. When you pull WB/WT high during reset, you promise the processor to support the more complex L1WB snooping protocol (in the Intel PODP/DX4-WB variation, not in the Cyrix variation). In case of the SiS471 chipset, the L1WB protocol is activated by a combination of jumpers to select the cache coherence protocol and a configuration bit to repsond to write back cycles. Furthermore, the L1WB protocol signals and INV and HITM need to be connected between the processor and the chipset. Your mainboard is too old to support the DX4-WB pinout, so you need to re-route some signals. http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm has a comprehensive overview on 486 pinouts. Your board supports the PODP, so it is able to interpret the signals sent by an 5x86, but it requires to receive them on pins on the outer row that is not present on the 5x86. Instead, the AMD 5x86 sends them on pins that the Cyrix 486 processors use for different purposes. Supporting L1WB thus means you have to disconnect the pins from their cyrix functions (cut traces) and re-wire them to the DX4-WB/5x86 functions, by connecting them to the corresponding PODP pins.

I'm not familiar with this ABIT board, but would it be more likely that those Cyrix-specific pins are at least routed through jumpers so that you can disconnect them, and not hardwired? IIRC that's how it worked on that SiS 471 EFA board I have, where there are jumpers for WB# and HITM# and so forth, but the problem was the outer P24T and inner P24D pins for the same functions were not wired together.

Thanks a lot for the (valuable!) info.
I was tricked here, because the L1 cache benchmark is better with my "enabling attempt", but this could have other reasons.
The "WB_enable" pin is indeed routed to a jumper, but as for the other signals I´ll have to check closer tomorrow. (There are many so far unpopulated and unused jumpers left btw.)

I always wondered why some 5x86 ready boards had loads of jumpers and all of them needed to be jumpered correctly to finally enable WB. And here we have the reason!
At least I won' t have to tinker with the AWARD BIOS anymore.

Edit:
The relevant pins of the PODP pinout (INV, CACHE, HITM and WT/WB) all go to (unpopulated) jumpers.

The AMD DX4WB / 5x86 ins are as follows: pin B13 (WB/WT) is routed to a jumper, B12 (CACHE) and A12 (HITM) are grounded, A10 (INV) is connected to Vcore.
Since the ground- and Vcore connections are happening in some in-between layer this won´t be easy to fix.

I guess this is a case for Sphere´s" interposers...

majestyk wrote on 2023-02-27, 20:01:

pin B13 (WB/WT) is routed to a jumper,

which is likely meant to send the reset signal to Cyrix's WM_RST ("warm reset") on B13, instead of the standard hard reset pin C16. A 5x86 has a similar signal called SRESET ("soft reset") on pin C10. A board supporting the DX4-WB/5x86 pinout would have a way to jumper the runtime CPU-reset there, too. The problem with the standard RESET signal is that is clears the complete L1 cache. In L1WT scenarios, that's just a performance issue if you are resetting the processor often (think 286 software exitting the procted mode via CPU reset), but the performance loss caused by the reset is likely negligible to the other overhead of resetting the processor. On the other hand, on a L1WB chip, you will lose the data in dirty L1 cache lines if you apply RESET during operation. That's why for completely proper operation of a L1WB 486 system, the reset caused by the keyboard controller must not be routed to RESET, but needs to be routed to WM_RST/SRESET.

If you take a look at the AB-AH4 jumper manual on The Retro Web, you will find that the jumper pin you mentioned for B13 is only covered by a jumper in the Cyrix 486 setting. When looking at that table, please note that the Cyrix 486 / Cyrix 5x86 distinction is slightly oversimplified. Late Cyrix 486 processors (mostly low-voltage ones, especially the DX4) used the Intel DX4-like pinout called "Cyrix 5x86" in that table, as did the Cyrix 5x86. Those processors work with AMD 5x86 / Intel Enhanced DX2/DX4 jumpering, not with the Cyrix jumpering. Typically, those Cyrix processors are marked with "Standard Pinout" on the ceramic case - which you don't see if you have the version with the aluminum heatsink glued to the case.

"B13" is connected to pin 3 of jumper 15. With the jumper in position 3-2 it can indeed be connected to pin 102 = WM_RST = INIT of the 85C471.
I´m using pin3 for pullup now and skipped the jumper. The WT/WP pin is now pulled high permanently.

I managed to route the signals "CACHE" (=PCD in the SIS datasheet) and "HITM" from the 5x86 pins to the respective chipset pins via jumpers that had to be populated. (pictures will be added soon).

The "INV" pin A10 connects to pin 2 of JP13 (that also had to be populated) it can be jumpered 1<2 to connect to Vcc (rather pointless here) or 2-3 for a connection to pin 1 of Jp25.
Bridging jumper 25 1-2 connects CPU-INV input to the "W/R" output of the CPU (N17) and at the same time to pin 104 (W/R) of the 85C471 (where W/R is I/O). Not sure if this connection makes sense or causes problems...
With this configuration the system stops at the POST summary screen with a blinking cursor beside the LPT port.

I cannot find any "INV" pin at the 85C71. Here´s the datasheet:

majestyk wrote on 2023-02-28, 11:40:

The "INV" pin A10 connects to pin 2 of JP13 (that also had to be populated) it can be jumpered 1<2 to connect to Vcc (rather pointless here) or 2-3 for a connection to pin 1 of Jp25.
Bridging jumper 25 1-2 connects CPU-INV input to the "W/R" output of the CPU (N17) and at the same time to pin 104 (W/R) of the 85C471 (where W/R is I/O). Not sure if this connection makes sense or causes problems...

I cannot find any "INV" pin at the 85C71.

Connecting INV and W/R makes a lot of sense. INV is meant to tell the processor whether it should INValidate the L1 cache contents (INV=high), because a busmaster writes (W/R=high), or it needs to write back the L1 contents (INV=low), because a busmaster reads (W/R=low). Having separate W/R and INV pins on the processor allows for advanced mainboard chipsets that can run cache snoop cycles (using INV) in parallel to an independent data transfer cycle (using W/R). The SiS 471 is not that advanced and is designed to be used with INV=W/R.

After checking all jumpers and connections that are involved in L1 WB mode and finding absolutely no errors I found out that pulling WB/WT up with 10K or less is necessary to enable WB at reset (values higher than 20K don´t enable WB safely).
Then I was confronted with the same garbled screen at DOS-prompt as in the very beginning.

Out of a hunch I started testing different BIOSes for this chipset. All of them either crashed or in the best case had the same results.
All of them were AWARD ones so I finally tried the latest AMI BIOS from 1994 and all problems were solved:
https://theretroweb.com/motherboard/bios/ah4. … 89873319274.zip

I can enable AND disable both L1 and L2 and I can enable WB for L1 like it should be.
In Speedsys CPU score went from 42.75 to 49.46, the memory performance scores went from 69.71/36.52/ 22.90 to 109.55/36.17/23.75

Seems like all the AWARD BIOSes fail to tell the chipset to use L1WB and the chipset sabotages WB although all signals are jumpered / wired correctly and WB is enabled at the CPU.

All the necessary jumpering IS provided on this mainboard (but you have to add lots of jumper-pins). Only pulling up "B13" at the CPU needs to be done with an additional resistor.

Here´s the working jumpering for this setup, added jumpers have blue colour.

Note that this is one of the mainboards where you have to put a jumper on the "Turbo Switch" header (pins 2-3) to have full speed, otherwise you´re in permanent "Turbo" non-speed.

Besides the essential link given above by 'mkarcher'
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm
there´s also additional information to be found on Jan´s page:
http://web.inter.nl.net/hcc/J.Steunebrink/amd5x86.htm

majestyk wrote on 2023-03-01, 10:58:

Seems like the all the AWARD BIOSes fail to tell the chipset to use L1WB and the chipset sabotages WB although all signals are jumpered / wired correctly and WB is enabled at the CPU.

Yeah, the BIOS is supposed to use the CPU ID to enable the L1WB protocol support in the chipset. If the BIOS doesn't recognize the 5x86 CPU ID, it won't set the WB protocol enable bit, which can cause the same issues as missing traces for the WB pins. See page 23 of the PDF file you attached, register 50, bit 4. The bios must set this bit if a processor in L1WB mode is installed, or strange things will happen.

The BIOS code disables the WT/WB option and masks it in the chipset setup table as soon as there´s not a Cyrix CPU detected (I haven´t tried DX4-WB ones so far), overriding other BIOS mods / settings. (In the AWARD BIOSes 5 of the 8 bits of register 50 are "X-ed").

On the mainboard´s flipside theres was not much to do, just adding two resistors, no need to cut any traces:

Hi majestyk,

In addition to mkarcher’s excellent information, I like to contribute some info about the BIOS on this AB-AH4 board.

I’ve looked into your Award 08/30/95-SIS-85C471E/G-2C4I9A12-02 BIOS and found precisely what mkarcher writes: this BIOS has no support for the Am5x86-133 and won’t set the WB protocol enable bit in the chipset.
If you had set the Am5x86 multiplier to x3 mode it would have worked though. The BIOS will recognize the Am5x86 as an Enhanced Am486DX4 then, a CPU it supports including L1 WB.
But of course this is not why you installed an Am5x86-133. 😉

I’m amazed that the 1994 AMI BIOS works with the Am5x86 in L1 cache WB mode, but if you like to try an updated Award BIOS, I have one!
Many years ago I helped a guy running an Am5x86 on his Abit AB-AH4 and adapted an up-to-date 11/28/95 SiS471 BIOS for this board. He successfully ran his Am5x86 at 160MHz and L1 WB mode with this BIOS. Here is a copy:

Being a late 1995 BIOS, it is free from the Year 2094 and 2GB Harddisk display limit bugs, and fully supports the Am5x86 and Cx5x86 CPUs, and Harddisks up to 8GB.
You can Enable/Disable the L1 and L2 cache separately from the BIOS, but the L1 WB/WT option is again automatic.
This BIOS shows the “L1 cache: WB/WT” option in the BIOS Setup only for the P24T and for Cyrix CPUs.
For the P24D (486DX2WB), Am486DX4WB and Am5x86, this 11/28/95 BIOS can detect if these CPUs are in WB mode and programs the chipset registers accordingly. It then hides the “L1 cache: WB/WT” option, because user interaction for this automatic function is not required.

Cheers, Jan

Thanks a lot, Jan!
I will try this AWARD version tomorrow and will also try 4 x 40MHz and report the results. (VLB graphics will be more difficult of course.)
Generally I prefer AWARD over AMI, but I know there are exceptions to this rule when AMI does the trick.

Still no luck with AWARD 🙁
I tried version "AH4_J1" and the system hangs right before finishing loading DOS from floppy.

majestyk wrote on 2023-03-02, 09:06:

Still no luck with AWARD 🙁
I tried version "AH4_J1" and the system hangs right before finishing loading DOS from floppy.

This floppy boot hang still looks a lot like a L1 cache WB coherency problem.

For the Am5x86, the SiS471 chipset needs to work in the Intel POPD/DX4-WB protocol and this is set by 2 hardware trapping jumpers. The SiS471 datasheet indicates this setting on page 22.
The Hardware Trap Definition of the DACK1* and DACK0* pins should be as for the P24D/P24T, so both these pins must be connected to a 2K2 pull-up resistor.
Although only the Intel 486DX2WB (P24D) and POPD (P24T) are mentioned, this setting is also needed for the Intel 486DX4WB, Enhanced Am486DX2, Enhanced Am486DX4, and Am5x86.

As the DACK1* DACK0* hardware trapping has to be set differently for other CPU models, I expect the jumper pins for this to be populated on any SiS471 board. At least they are on my Chicony CH-471B. 😉

Hopefully setting these 2 jumpers to the P24D/P24T position will fix the issue.

Jan

Thanks! Will check these settings thoroughly.

(Forgot to mention the system boots with L1 disabled.)

One more question about the "CACHE" and "PCD" signals:
The SIS datasheet says

PCD is an input for the 85C471. On the CPU side the 5x86 has both a "PCD" (output) and a "CACHE" (output) pin. On the ABIT AB-AH4 I can either jumper PCD (chipset) to connect to the PCD-pin (CPU), then the system works, or to connect it to the CACHE pin (CPU), then the system hangs at POST summary screen. The latter seems kind of logical but won´t work.

Chkcpu wrote on 2023-03-02, 10:52:

...Hopefully setting these 2 jumpers to the P24D/P24T position will fix the issue.
Jan

Yes it will!
One of the DACKs was set to "pull down" (jumper 21).

After correcting that, the system would hang at POST summary screen like it did before when chipset "PCD" was connected to CPU "PCD". After jumpering chipset "PCD" to connect to CPU "CACHE" (as I always thought it should be) all is well. Memory benchmarks have improved even further: 117.62/50.99/31.10

The new jumpering:

I will now program the EPROM with your AWARD version.

Thank you very much indeed, Jan!

Okay, this is great news! 😀

Yes, it makes sense indeed, to connect CPU “CACHE*” to Chipset “PCD” because this chipset pin 118 changes function to “CACHE*” when both DACKs are pulled high.

I use the same jumper settings when running an Am5x86 in L1 WB mode on my SiS471 board;
- CPU “CACHE*” to Chipset “CACHE*” (PCD)
- CPU “HITM*” to Chipset “HITM*”
- CPU “WB/WT*” pulled high
- but I have CPU “INV” unconnected.
It works fine that way, but it may not be set for optimum performance. I need to experiment more on how to connect the INV signal and if connecting it to W/R* works better.

One remark about the AH4_J1 BIOS, the Am5x86 support in this 11/28/95 SiS471 BIOS is great, but this BIOS doesn’t support the Secondary IDE port. So only a Primary Master and a Primary Slave drive are supported.
Under Win9x this is no problem, but if you need 4 IDE drive support in DOS, I could try to patch the original AB-AH4 08/30/95 BIOS because it supports both Primary and Secondary IDE ports.
This would involve adding Am5x86 support including the x4 multiplier and fixing the 2GB HDD display limit bug, so this may take some time… 😉

Jan

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Question about the speedsys' graph - shouldn't we see the blue line (write speed) also represent difference between L1 and L2 cache "space" when write-back is enabled?

Chkcpu wrote on 2023-03-02, 19:17:

...One remark about the AH4_J1 BIOS, the Am5x86 support in this 11/28/95 SiS471 BIOS is great, but this BIOS doesn’t support the […]
Show full quote

...One remark about the AH4_J1 BIOS, the Am5x86 support in this 11/28/95 SiS471 BIOS is great, but this BIOS doesn’t support the Secondary IDE port. So only a Primary Master and a Primary Slave drive are supported.
Under Win9x this is no problem, but if you need 4 IDE drive support in DOS, I could try to patch the original AB-AH4 08/30/95 BIOS because it supports both Primary and Secondary IDE ports.
This would involve adding Am5x86 support including the x4 multiplier and fixing the 2GB HDD display limit bug, so this may take some time… 😉

Jan

Personally I´m o.k. with one IDE channel, but when someone would use a VLB-IDE controller that doesn´t bring it´s own BIOS this could be a limitation. (An ISA SCSI-controller would probably have inferior performance.) So if you have some spare time one day, it might be worth giving it a try.

GigAHerZ wrote on 2023-03-02, 20:39:

I have a QDI board with the same chipset and with 5x86 running at 3x50MHz. So this thread is very interesting to me.

Question about the speedsys' graph - shouldn't we see the blue line (write speed) also represent difference between L1 and L2 cache "space" when write-back is enabled?

Wow - are you running 50 MHz FSB with a VLB video card? If so, which one is it?

Isn´t the higher throughput for memory writes rather a matter of "Write Policy" / Write Allocation" than "Write Policy" /Write Back? Early Intel and AMD CPUS lacked some of the features.