Not sure where I am going to find help on this. My program sets up an ISR on 0x1C timer that watches the interrupt vector table for any changes to the SoundBlaster IRQ. If it detects a change, it changes it again pointing to my own ISR, and I make an I/O write to the pcmcia card to set a register that indicates the TSR is ready and has control of the IRQ.
The problem is, when I set that flag to indicate I am ready this will almost always result in an interrupt being triggered at that exact edge of the i/o write by the soundcard, and I do not always see that first interrupt that comes in while I am in the 0x1C ISR. When that happens it means the DMA transfer does not start and has about the same symptom as configuring the game with the wrong DMA, it will not pass initialization. if it does catch that first IRQ It will properly play the entire cycle no issue, and continue fine until the game/application unhook/hooks the IRQ again for any reason and then it is the same game of chance if I see the first interrupt.
I have played around with disabling/enabling interrupts inside the 01xC ISR, clearing/settings the interrupt flag, making sure irq is unmasked before setting my hardware flag etc. Is there no way to have the IRQ5 ISR preempt the 0x1C ISR? is that even my issue? that is the question I am trying to answer for myself.
I've started looking at the SoftMPU code to see how it handles different interrupt situations and see if I cannot by mistake learn something to help my issue.
So the issue may be unrelated to my software handling of the interrupts and is in fact related to my pulse width for the IREQ during DMA's being not quite long enough some times causing it not to register. I realized this after seeing that the interrupt was not even getting to the ISA bus out of the PCMCIA Controller. So I will look at easiest way to update my GAL equation to fix this if I can, without adding any hardware.