Reading the whole thread again makes me think of this another way.

Say, you take a standard K6-3+ as base and you manage to get the original design. It was kooked with the 180nm process.
If you would kook one at say 45nm (which is prehistoric today as well) the chip may be able to run at 1,3v and 900MHz. Then it only needs a bit volt converter, more L2 cache and different multiplier interpretation and all should be well.

Take any S3, S7 or 370 CPU and fill in the same...

Sounds easy, probably is less easy... But mighty be possible (but definitely not by me)

BitWrangler wrote on 2021-11-09, 23:11:

Jasin Natael wrote on 2021-11-09, 17:33:

Interesting idea, but I just don't see it being realistic. Microarchitecture from even 25 years ago is crazy complicated. It mi […]
Show full quote

Interesting idea, but I just don't see it being realistic.
Microarchitecture from even 25 years ago is crazy complicated. It might seem archaic compared to the latest and greatest you find in your new smartphone or gaming console, and it is.
But it is still by and large way out of reach of the average person without some serious intellect, R&D costs and access to the right materials and manufacturing.

Think of it this way, a basic internal combustion engine is relatively simple in mechanics and operation.
Most people can understand the basics, air/fuel in, sparks makes fire, combustion/compression stroke valves open to either allow or exhaust air. This drives the rotating assembly so on and so forth.
Most people with the right tools and training and can work on these or even assemble these from parts with relative ease.

However almost no one out there can manufacture engine blocks /cylinder heads, camshafts and pistons to the extremely precise tolerances needed for them to be usable.
This takes raw resources as well as tons of understanding how to actually cast or forge the parts. Only special machine manufacturers are able to do this for a reason.

And microarchitecture is far, far more complex than internal combustion engines.

The hobbyist who is furthest ahead on this, with a chip foundry in his garage, is about ready I think to do something like a 4004, in 5 years he might be up to 8080.

Well that is progress. The 4004 was released in when, 1971? Might take a minute to reach the 486 era.....

waterbeesje wrote on 2021-11-10, 14:23:

Reading the whole thread again makes me think of this another way. […]
Show full quote

Reading the whole thread again makes me think of this another way.

Say, you take a standard K6-3+ as base and you manage to get the original design. It was kooked with the 180nm process.
If you would kook one at say 45nm (which is prehistoric today as well) the chip may be able to run at 1,3v and 900MHz. Then it only needs a bit volt converter, more L2 cache and different multiplier interpretation and all should be well.

Take any S3, S7 or 370 CPU and fill in the same...

Sounds easy, probably is less easy... But mighty be possible (but definitely not by me)

I could be wrong but I don't think that the limitation of the clock speed scaling has only to do with voltage and heat dissipation.
I'm no expert but I think that things like pipeline stages and branch prediction, cache coherency and other more complex things that I don't really understand would be the limiting factor here.

High level Pipelining is a way to deal with in-die latency alongside performance issues

AKA Distance is speed, the smaller the distance the greater the speed if several components need to communicate with a common sub system at the same time they can end up out of sync, pipelining can remove some of the signalling issues

There has been an argument that a simple non-pipelined CPU with only thousands of transistors has a hard speed limit regardless of how much you shrink the die/process, from what I can tell this is mostly false.
Just a bit of a thought process but a 286 cpu actually has fewer transistors than a single functional unit within a single stage of a single pipeline, ergo following proper design practices a simple non-pipelined cpu should be able to at least operate at the same GHZ speed as said pipeline due to the internal latency within the die being less than the pipeline unit itself

Intel is doing that sort of thing through their Custom Foundry business, though it remains to be seen what exactly will come out of that business venture, as it's not really even started yet. As shown by all the retro component builders, there is certainly a demand for old hardware on new designs and new hardware on old designs, and there is certainly a big demand for keeping old industrial/Enterprise hardware in play, due to the fact that many old industrial machinery and such only work with specific software and hardware that doesn't run on today's systems, which is why there is a thriving industrial/embedded PC market that will benefit from customized CPUs. Would you pay for a brand spankin new retro PC with accurate custom-built hardware that performs and exceeds something from 25 years ago, with the added benefit of today's superior tech applied to it's fabrication and components? I would and certainly, others would too.

BitWrangler wrote on 2021-11-09, 23:11:

Jasin Natael wrote on 2021-11-09, 17:33:

Interesting idea, but I just don't see it being realistic. Microarchitecture from even 25 years ago is crazy complicated. It mi […]
Show full quote

Interesting idea, but I just don't see it being realistic.
Microarchitecture from even 25 years ago is crazy complicated. It might seem archaic compared to the latest and greatest you find in your new smartphone or gaming console, and it is.
But it is still by and large way out of reach of the average person without some serious intellect, R&D costs and access to the right materials and manufacturing.

Think of it this way, a basic internal combustion engine is relatively simple in mechanics and operation.
Most people can understand the basics, air/fuel in, sparks makes fire, combustion/compression stroke valves open to either allow or exhaust air. This drives the rotating assembly so on and so forth.
Most people with the right tools and training and can work on these or even assemble these from parts with relative ease.

However almost no one out there can manufacture engine blocks /cylinder heads, camshafts and pistons to the extremely precise tolerances needed for them to be usable.
This takes raw resources as well as tons of understanding how to actually cast or forge the parts. Only special machine manufacturers are able to do this for a reason.

And microarchitecture is far, far more complex than internal combustion engines.

The hobbyist who is furthest ahead on this, with a chip foundry in his garage, is about ready I think to do something like a 4004, in 5 years he might be up to 8080.

DIYing a 4004 is actually quite impressive

waterbeesje wrote on 2021-11-10, 14:23:

Reading the whole thread again makes me think of this another way. […]
Show full quote

Reading the whole thread again makes me think of this another way.

Say, you take a standard K6-3+ as base and you manage to get the original design. It was kooked with the 180nm process.
If you would kook one at say 45nm (which is prehistoric today as well) the chip may be able to run at 1,3v and 900MHz. Then it only needs a bit volt converter, more L2 cache and different multiplier interpretation and all should be well.

Take any S3, S7 or 370 CPU and fill in the same...

Sounds easy, probably is less easy... But mighty be possible (but definitely not by me)

That’s a good idea, not sure how we would get the specs of the design though 🙁

An FPGA CPU would be hard pressed to out perform existing Pentiums on socket 5. On socket 3 and lower you have to deal with interfacing the 5V bus. But what about using an FPGA to adapt a newer CPU to the older socket 5/7/370 bus? In other words, the FPGA would handle differences in bus protocol or missing signals. Might be possible, without having to manufacture custom silicon. Upgrade all your old Pentiums to a 2GHz Pentium M 😀

rmay635703 wrote on 2021-11-10, 19:41:

High level Pipelining is a way to deal with in-die latency alongside performance issues […]
Show full quote

High level Pipelining is a way to deal with in-die latency alongside performance issues

AKA Distance is speed, the smaller the distance the greater the speed if several components need to communicate with a common sub system at the same time they can end up out of sync, pipelining can remove some of the signalling issues

There has been an argument that a simple non-pipelined CPU with only thousands of transistors has a hard speed limit regardless of how much you shrink the die/process, from what I can tell this is mostly false.
Just a bit of a thought process but a 286 cpu actually has fewer transistors than a single functional unit within a single stage of a single pipeline, ergo following proper design practices a simple non-pipelined cpu should be able to at least operate at the same GHZ speed as said pipeline due to the internal latency within the die being less than the pipeline unit itself

It's not that there is a hard speed limit, just a question of diminishing returns. Pipelining breaks up time-consuming operations into simpler ones that run in parallel. You'll have more transistors but since they are acting in parallel instead of in series the clock speed can go higher. If you have a design where you read data from a register, modify it, and then store it back, all within one cycle, you can shrink it all you want but it will always have a slower clock period compared to a design that reads the data a cycle early, modifies it in the next cycle, and stores it back in a third cycle.

bakemono wrote on 2021-11-11, 06:17:

An FPGA CPU would be hard pressed to out perform existing Pentiums on socket 5. On socket 3 and lower you have to deal with interfacing the 5V bus. But what about using an FPGA to adapt a newer CPU to the older socket 5/7/370 bus? In other words, the FPGA would handle differences in bus protocol or missing signals. Might be possible, without having to manufacture custom silicon. Upgrade all your old Pentiums to a 2GHz Pentium M 😀

rmay635703 wrote on 2021-11-10, 19:41:

High level Pipelining is a way to deal with in-die latency alongside performance issues […]
Show full quote

High level Pipelining is a way to deal with in-die latency alongside performance issues

AKA Distance is speed, the smaller the distance the greater the speed if several components need to communicate with a common sub system at the same time they can end up out of sync, pipelining can remove some of the signalling issues

There has been an argument that a simple non-pipelined CPU with only thousands of transistors has a hard speed limit regardless of how much you shrink the die/process, from what I can tell this is mostly false.
Just a bit of a thought process but a 286 cpu actually has fewer transistors than a single functional unit within a single stage of a single pipeline, ergo following proper design practices a simple non-pipelined cpu should be able to at least operate at the same GHZ speed as said pipeline due to the internal latency within the die being less than the pipeline unit itself

It's not that there is a hard speed limit, just a question of diminishing returns. Pipelining breaks up time-consuming operations into simpler ones that run in parallel. You'll have more transistors but since they are acting in parallel instead of in series the clock speed can go higher. If you have a design where you read data from a register, modify it, and then store it back, all within one cycle, you can shrink it all you want but it will always have a slower clock period compared to a design that reads the data a cycle early, modifies it in the next cycle, and stores it back in a third cycle.

🤔 can you do it?

One CPU I could see being useful is a new s370 CPU, essentially a Pentium 3 but without the locked multiplier.

Perhaps at some point it could be even emulated, but put on an adapter to fit s370. probably wouldn't even need a classic heatsink anymore (think how Overdrives were made with onboard regulation).

Not very realistic, but having more easy access to unlocked s370 CPUs could make things easier already.

Would there really be any reason for a faster S370 CPU?

You already have up to 1.4Ghz which can be overclocked.

Past that, you can go to Socket A, which can net you up to around 2.3Ghz+ on a KT7A with a simple socket wire mod and modded BIOS.

Then if you want even faster with AGP and full ISA support, you can go with something like a PIAGP s478 or LGA775 system though the LGA775 SBC is impossible to find.

Now if you could have a CPU that could have very granular speed control on the hardware size... that would be excellent.

honestly I don't see the point of most of this outside of being a somewhat interesting exercise

now, the prospect of being able to fabricate a 8080 in my garage on the other hand would be way more interesting to me than paying intel for a short run CPU design or whatever

FPGA tech is cool but it's not magic. You'll be hard pressed to synthesize a soft CPU core running faster than ~200Mhz for the most part. Dreams of building 1Ghz processors using an FPGA are just that: dreams!

Where FPGA really does work is the old 8-bit / 16-bit vintage gear: it's straightforward to implement a 6502 or 8088 CPU plus all the supporting hardware, and it's even possible to do an 80486 core at 33-66Mhz on an affordable FPGA.

Asking Intel for new PIIIs is either going to turn into a laugh or trigger some P4 PTSD.
"not again!"

Maybe something like a Rise MP6, BGA on adapter?
PIII had cache Slot1 on two chips, upgrade was just the new core with L2 on die.
Real huge upgrades would probably require some core redesign(from a topological standpoint)/improvements?

I can't see designing new cpus but I do sometimes wonder what if and did a new run of k6-3 but at say 130 or 90nm, maybe increase l2 from 256k to 2mb. Or a new Pentium MMX but at 90nm with 2mb l2 on die and supporting 100mhz fsb. Or even via releasing the MVP3 chipset but now with the 686b Southbridge

Sphere478 wrote on 2021-11-11, 08:24:

🤔 can you do it?

If the idea is feasible it'll need a PCB design with FPGA, ZIF socket, voltage regulation, etc. and all of that is above my pay grade...

I found an interesting document though about connecting an FPGA to Intel CPUs: https://www.xilinx.com/support/documentation/ … tes/xapp196.pdf

At some point were limited by other factors like memory bandwidth on those platforms. So faster CPUs might enable you to play run more vintage software but it won't enable you to watch a bluray without skipped frames.

I was playing around for ahwile with those Broadcom MPEG4 decoders, the ones that are mini PCI-E. I was eventially able to use a Mini PCI-E to PCI-E 1 X to PCI adapter I made, install it in a PCI slot on my 0R840. What I learned was that with anything less than like a 9700 PRO and RDRAM 800 and Dual CPU, Your not going to be able to play a Blueray. But I was able to play a Blu Ray on a Pentium III like that. Using a Co-Processer, but you needed a extreemly fast PIII. Still forget modern web browsing even with Dual CPU and a webbrowser that can support mUlti thread its a miserable experience.

So I just think the whole Idea is waste of time, even considering, thinking about the idea, that if there was somone who could theretically make a faster socket 7, would they, and assuming they did, and you could get it to work, what the point would be, becasue your still not going to be able to really do shit. Atleast not way more than you can do now. So just why.

bakemono wrote on 2021-11-12, 05:11:

Sphere478 wrote on 2021-11-11, 08:24:

🤔 can you do it?

If the idea is feasible it'll need a PCB design with FPGA, ZIF socket, voltage regulation, etc. and all of that is above my pay grade...

I found an interesting document though about connecting an FPGA to Intel CPUs: https://www.xilinx.com/support/documentation/ … tes/xapp196.pdf

Interesting find :p I was expecting the wiring diagram to be far more complicated.. even if they aren’t including power in the schematic.

I heard of a dude back in the day, getting fed up of waiting for PODP to drop in price and managing to wire a pentium into/onto his 486 motherboard.... so there's only a few hundred jumper wires standing between your POD compatible 486 board and a K6 upgrade. 🤣

.. well and a lot of poring over bus, chipset and CPU pinouts, and figuring out if there's a minimum mode on K6s to run 32 bits wide and crap like that. (I actually have no idea how the 32/64 memory thing was handled or whether it was just a geek urban legend.)

BitWrangler wrote on 2021-11-12, 15:26:

I heard of a dude back in the day, getting fed up of waiting for PODP to drop in price and managing to wire a pentium into/onto his 486 motherboard.... so there's only a few hundred jumper wires standing between your POD compatible 486 board and a K6 upgrade. 🤣

.. well and a lot of poring over bus, chipset and CPU pinouts, and figuring out if there's a minimum mode on K6s to run 32 bits wide and crap like that. (I actually have no idea how the 32/64 memory thing was handled or whether it was just a geek urban legend.)

We need a gerber file for that adapter!