The jumpers are for the configuration of the correct cache size, not for adjusting to different pinouts.

Did you also replace the TAG-RAM chip (the 9th chip) with the correct size - 64Kx8 or 128Kx8?

To rule out any faulty chips among the 1024K ones, you can test them in groups of 512K like this (you can also leave the original 32Kx8 TAG-RAM in place in this case:

Thank you for the hint, majestyk. Definitely this is one missing piece of the puzzle. I was not aware about the TAG-RAM chip. I have at hand a 9th ISSI chip of the same size that I could use as TAG-RAM.

However, before I potentially damage my mainboard, can you tell if the ISSI pinouts from the datasheet will work? Or have there been mainboards that were designed to work with only one SRAM manufacturer like Winbond in my case?

The different numbering of the I/O lines won´t matter. And having Vdd at the "chip enable 2" pin is probably correct.

If the system won´t post at all I´d rather suspect a single faulty chip.

Don't worry about the pinout. The ISSI datasheet you linked shows the standard pinout for 1MBit (128k x 😎 CMOS SRAM expected by any 486 mainboard supporting 1MB cache from DIP chips. If you compare the pinouts, pay attention to the extra pins of the 32-pin chip, so all pin numbers are "off by 2". If you now compare the the Winbond 257 pinout and the ISSI 1024 pinout, they mainly use a different naming convention (Vss = GND, Vdd = Vcc (+5V), CS (chip select) = CE (chip enable)). The 32-pin chips have a two-way chip enable / chip select. They are only enabled if CE1 is low (that's why there is a bar over the name), and CE2 is high. The mainboard applies +5V to pin 28/30, so Winbond-VDD aka ISSI-CE2 is high. The extra two address (A15, A16) lines on ISSI-2 and ISSI-31 are wired to address bits that are not used with 256kB cache.

The usual symptom of bad cache memory is a lockup of the system after the POST, because the POST (mostly) runs with L2 disabled. No POST at all points to a more severe problem than just unreliable bits in the cache. If one chip suffered sufficient ESD damage, you might have data or address lines shorted to +5V, ground or against each other. This is consistent with a no-POST-at-all situation. I agree with the suggestion to try different sets of 4 of your ISSI cache chips (check your tag! if it is a 256kBit type, re-use the known good tag. If it is a 128kBit chip, it needs to be replaced by one of the known-good Winbond 257-type chips).

You were both right. Summarized notes for anyone who encounters the same problem:

- I missed the whole thing about exchanging the additional TAG-RAM chip (9th DIP).
- I tested with a set-of-4 chips setup as suggested. One of the ISSI chips turned out to be damaged / non-functional.
- The different pinout (IO line numbering) does not matter. The Winbond pinout can be replaced by the ISSI pinout without any trouble.

Lucky me has ordered 10 chips, so I now have a working system with 8x L2-cache chips + 1x TAG-RAM chip. Problem solved.

Thank you for your help, majestyk and mkarcher 😀

Gonduron wrote on 2021-12-30, 18:27:

One of the ISSI chips turned out to be damaged / non-functional.

...

Lucky me has ordered 10 chips, so I now have a working system with 8x L2-cache chips + 1x TAG-RAM chip. Problem solved.

It's well known in the community that the market is flooded with fake ISSI chips (initially, they were mostly marked -10N, a speed grade never produced in DIP case by ISSI, according to ISSI employees) with a typical dead-on-arrival rate of around 10% (just as you experienced). It seems like they label them at -12N or -15N now, to be less suspicous. Don't worry about the likely fakeness, though. The experience with the ones that are not dead on arrival is generally good. "Fake" doesn't mean non-functional in this case, just "they were not released by ISSI after proper quality assurance as original devices".

Just a quick remark for you, as you want to make the board running in top speed: I've not seen any SIS471 board+bios combination, where L2 cache properly works in write-back mode.
For that, you can edit the bios or download modified bios by someone else, which changes few registers to make L2 cache properly work in write-back mode.

As usually bioses seem to be interchangeable as long as the chipset is same, you can get this one: Re: QDI V4S471/G locks up with 1024kB of cache [Fixed! Nicer Award BIOS available!]
I searched for the latest SIS471 based bios i could find and then modified it to have both all options available to change in bios and fix the L2 write-back mode.

Hey GigAHerZ, thank you for the hint. I've already stumpled on the dirty tag issue in this post: 486 cache/ram speed issue with write-back

I checked my BIOS with CTCM already, and as you hinted, it shows my mainboard suffers from it too. I'll get back to this topic later once I have solved more pressing issues. Next steps in my retro-PC build will be integrating three different sound cards and mixing them up to one Line-out.