Never tried out the PA-2012, but earlier FIC Via-based boards (like the PA-2010+) happily ran at 75 and even 83MHz, so would be surprised if this one didn't.

Do you have another So7 CPU? I'd suspect issues with the voltage mod given what you describe. Pretty much any other CPU would be able to rule that out, even if it's a P54C, just run it at 1.5x 75MHz and see what happens. If same issues, it's bus speed. If not, it's the K6-2 and likely the voltage it's getting.

I just tried a Pentium-S and a Pentium MMX 233 - all at unmodded voltages and multi x 1.5 or x2. All of them POST at 66 MHz, not at 75 MHz.
Even a Tillamook POSTs and is reported correctly under 66 MHz (2.1V) and sometimes under 75 MHz.

Interesting. If it was a power decoupling capacitor then there wouldn't be a resistor there. The 33 ohm resistor suggests it's a clock output, so it seems a bit odd to have a capacitor on a clock. But maybe the clock driver is too strong and was driving up faster than needed, which would create more EMC noise. So they use the capacitors to take out the harmonics leaving just the sine wave of the fundamental? Might also help control any overshoot and ringing. In which case the capacitor value would be tiny, I'd guess very low nano, possibly mid pico.

A few things that might be worth trying. I can't find the datasheet for this part, but looking around it seems the FS6231 was a matching part. I also can't find that. But did find the FS6232, which I did find a datasheet for. It's not the same (56 pin vs 58 pin), but it looks sort of similar. The PCI clock outputs are all on one side and the other clocks on the other side. So it's likely that those other purpleish looking caps on the other side of the clock gen to your missing cap (C150-C170 block) are the same value, or close to, and go to the PCI slots. So check with a meter for a connection between the clock pin on a random slot and each of the capacitors (side nearest the resistors). If you find one that's shorted to the PCI clock, then remove that capacitor (measure it if possible) and fit it to the missing one. See if that makes things work, and don't use the PCI slot that donated the capacitor. Then just replace the PCI one later.

The other is to guess the value. Impedance of a capacitor is 1/(jwC), w=2*pi*f. And we're not bothered about the phase element, so I think we can drop the j. Line impedance might be around 30 ohms (based on what I think is the source termination resistor). We don't know which clock line this is, so let's say we want to decrease the signal by at least ~50% for all frequencies above 100MHz. So that'll give 30=1/(2*pi*100MHz*C), which gives C~=5*10^-11, which I think is 50pF. May be best to err on the small side, so maybe 10pF?

Last thing I can think of, the clocks on that side are all supposed to be balanced pairs, so really C151 (the missing one) should be matched with C147 (the one above it). So remove C147, measure it, and get some the same value, then fit new caps to C147 & C151 (in case the measurement was a bit off, at least they'll be off the same amount). Might also be worth changing C152 & C155 at the same time if it looks like they might have been damaged by whatever took C151 off.

Thanks a lot!
The PCI-clock lines (pins A16) go to the smaller resistor/capacitor block between clock-gen and south-bridge.

And I found there´s a connection between the two 33R resistors connected to C151 andC152. There´s a trace connecting the contacts on the side that´s connected to pin 40 of the clock-gen:

This could mean the clock output from pin 40 feeds two different "consumers" and one of the lines lacks the damping capacitor.

I will transplant one of the purpelish caps from a PCI-slot bus line to this position later.

OK, that sounds like a convincing motherboard FSB issue.

Trick would now be to isolate it - if you know which component is the issue youmight be able to do something about it. Given you've already tried lots of VGA options, it's probably not that (most cards will happily work at 37.5MHz PCI or 75MHz AGP), and RAM seems safely ruled out as well. IDE is notorious for not liking overclocking, but it would fail at loading OS in that case, not right at beginning of POST. I'd suspect L2 cache most at present. Try disabling that in BIOS and seeing what happens at 75MHz. In fact, try disabling all integrated peripherals too. If it POSTs reliably after that, turn them back on one by one until you find the offending part.

Good spot on those outputs being linked, I wonder how that works with the balanced pair. Or if the FS6232 is different from the FS6231 and they're not balanced pairs.

If you've got a component tester, try measuring the value of the PCI capacitor when you try moving it. PCI clock and FSB clock might need different capacitor values. Decoupling caps don't normally matter about their exact value (0.1uF, 1uF, probably still works), but this is getting in to the analog side of things where values matter. Too small and not enough damping, too big and the signal is lost.

The capacitor will also shift the phase of the clock slightly, so will change the timings of when the clock edge arrives. Which might matter as well. I never got on well with analog stuff. Each thing you change has multiple effects.

Disabling all the peripherals and L2 cache makes no difference.

I have removed and measured C 155, it´s capacity is 25pF - then I soldered 2 x 27pF in position C151 and C155, but could not find any improvement. The best chances to boot into 75 MHz is with both capacitors OUT.

This datasheet for the W48S87-04 seems to come very close to the W48S67-04H (at lest they both have "04" at the end).

Boo.
Don't know if it will matter, but is C155 the 8th one down? If so, then it looks like that's got a 39 ohm termination resistor rather than the 33 ohm that the 5 above it have. Could be that those are for different clock speed, with different value capacitors? If the S87 is similar in pinout then it's an SDRAM clock rather than CPU.

Hmm, getting a bit desperate, but what happens if you take off all the CPU (144,145,147,151,152) capacitors? Looking at the photo for the PA-2013 on UR, that board has pads for the capacitors, but they're not fitted: https://www.ultimateretro.net/motherboard/ima … e1011167499.jpg Maybe they were having problems getting the 2012 through EMC testing and had to limit the maximum CPU clock to get it to pass.

Spread spectrum turned off?

On a slightly related note, but not actually useful in this case, I came across a cross reference chart for some clockgen chips.

Oops, sorry - I think I mixed that up, C151 (6th one down) was the one missing.
C152 ) (7th one down) is the one I removed and measured. Both have 33R resistors that are connected to pin 40.
I disabled "Spread Spectum" (as I always do).
It´s a pity I can´t test the clock signals with my scope, it´s an old 20MHz model.

And another observation: The northbridge doesn´t get hot at all just maybe 25-30°C, but when I "deepfreeze it" at the center of the package the system is up and running a second later - this effect is 100% reproducable.
Maybe the clock signal´s amplitude is too low, or the northbridge itself might be the problem.
It seems like the system is operating at some tipping point - sometimes it works, sometimes it won´t. Small changes of the setup can decide what´s happening.

If you wanted to poke at the VT82c597 then the clock lines are on P5 (Host CPU) and W5 (PCI). The datasheet says that the Host clock input should be on the same net as the CPU clock input (maybe that's the clock line that splits back at the generator), and that the PCI has to be 1/2 Host (so no asynchronous modes). It does also say the maximum supported speed is 66MHz.

I think (and I'm very hazy on the details, it's been a while since I knew some of this) that with source series termination (putting the resistor at the start), the bigger the resistor the lower and slower the signal is. For a given voltage in to a bigger resistor, less current will flow, so it'll take longer to charge up the line capacitance and the voltage is dropped over the resistor. But too small a resistance will lead to ringing. So if you're wondering if the signal level is too low you could always try dropping the resistor value. Of course, without being able to see the clock line (I'm the same, only have a slow digital scope) you won't really know if you're making things better or worse.

In the analog world this circuit is a (1st degree) low pass filter

The higher the values of C and R the lower it´s cutoff frequency.
For 33R and 25p I calculate a cutoff frequency of 193 MHz , so this should not damp a signal of 75 MHz too much, but it´s no digital function so the damping effect sets in way before the cutoff mark.
At the SDRAM-clock outputs there are 39R resistors, at the 4 CPU-clock and 4 PCI-clock outputs there are 33R resistors.

Maybe it´s worth a try testing without the capacitors. These are not mentioned in the Cypress datasheet, only the 33R 39R series termination resistors.

The CPU-clock output with the missing capacitor goes to the northbridge (after the trace has performed several loops).
The second (parallel) output goes to some CPU pin and at least two CPU-clock outputs go to the L2-cache SRAM chips that run at CPU speed.

While measuring DC values at the clock-generator I found Pin 2 ("REF0/CPU3.3") is tied to "high" via a 10K resistor.

This means at startup, when pin 2 acts as an input, the CPU clock outputs are set to be optimized for a buffer voltage (VDDQ2) of 2.5V. In fact VDDQ2 is connected to 3.3V power supply here.
Just wondering if this could have any negative effect when operating at a higher FSB like 75 MHz.

Odd. Don't know about this at all. Are pins 42 and 28 (VDDL) connected to 3.3V? The datasheet says all logic inputs have internal pull ups so if you want to try selecting 3.3V it'll need to be pulled low.

Only thing that jumps out in the datasheet when changing that pin is the rise and fall times. 0.8-3V/nS in 2.5V mode and 1-4V/nS in 3.3V. From skimming some older CPU datasheets the other day (386) I know there were quite strict rules about exactly how fast or slow the clock edge should be. So I think it's probably worth playing with.

Yes, both VDDL inputs are connected to 3.3V (there are 2 linear regulators for 3.3V on this board, one for SD-RAM and one for AGP. I think there´s no 2.5V voltage available on this mainboard.

Still doing some research here.

CPU-clock 0 from pin 44 goes to the AGP-slot (lowpass capacitor 4p7)
CPU-clock 1 from pin 43 goes to the L2-cache SRAM chips (lowpass capacitor 4p7)
CPU-clock 2 from pin 41 goes to the L2-cache SRAM chips (lowpass capacitor 4p7)
CPU-clock 3 from pin 40 goes to the CPU (lowpass capacitor 22p) and to the northbridge (lowpass capacitor removed)

I still don´t know if the removed cap was 4p7 or 22p. I had tried 22p but this worsened the situation. I´m going to try 4p7 next.

Just had a thought, though not immediately useful. Capacitance in parallel adds, so if CPU3 is driving 2 20pF capacitors, then that'll be 40pF, plus the PCB trace capacitance to ground plane, plus there's some output pin capacitance (I think 6pF from the datasheet). That's starting to sound like quite a load to charge up through the two 33 ohm resistors, given the W48S87-04 datasheet uses 20pF for the AC timings. It's possible the northbridge has different clock edge specification from the CPU, but I can't see that information in the datasheet. Back on the clock gen, I've also just spotted that the datasheet gives AC Output Impedance limits as 15-30 ohms. So I think driving two lines will be nudging the bottom end of that. High capacitance and low resistance might mean the output driver starts to hit current limits, which I think would slow the edge down. But them, increasing the resistor values would also slow the edge down and might make the signal quality worse.

Cache is disabled, isn't it? Might be interesting to borrow CPU2 by lifting R285 and seeing if R293 can be moved to go diagonally, so the CPU and northbridge have their own clock drivers. I know the northbridge says it should be on the same net as the CPU, but they're kind of not on the same net already (when the net splits at the source does that count?), and the CPU outputs are all off of the same PLL so they should be in phase. Should say that I don't know what the possible risks would be of doing this.

I just did some additional tests. Putting 4p7 as lowpass capacitor in the northbridge clock-line doesn´t make a difference.
I also changed the ("REF0/CPU3.3") input to pulldown, but that didn´t have any effect as well.
L2 cache is always turned off.

It´s also interesting to have a look at the traces on the flipside:

The red dots mark the northbridge trace that has a meander inductor (white box), the blue dots are AGP - also with a meander inductor (white box).
The two orange dots mark the 2 L2-cache clocklines, the red one is CPU clock that has a small meander inductor but goes as a straight trace until it reaches the CPU socket.

My conclusions for now are as follows:
1. we can rule out any defective components in the filters and traces between clock-gen and the chips they feed.
2. the missing capacitor has probably been removed in the factory, but replacing it won´t fix the 75 MHz instability.
3. There could be a problem with the northbridge clock-output signal caused by the generator output buffer - this could be tested by coupling the northbridge to the AGP output for example.
4. there´s still the fact that cooling down the northbridge with either a passive northbridge-cooler or using coolant spray fixes the issue perfectly for some time. The northbridge could also suffer some contact/solder defect due to a "flexing-issue" or sub-optimal soldering - it´s a "BGA"-chip after all. It´s also possible some (early) produced chips just weren´t capable of operating at 75Hz FSB, only when perfectly cooled, just like regular CPUS can be overclocked better/0nly under perfect cooling.

And another fun fact - If the clockgenerator´s F2 input is pulled down during startup you can select the higher frequencies. There are even soldering pads for the pull-down resistor.

I just tested 68.5 MHz that runs stable so far.

To be fair, the 82C597 blurb only specs it up to 66MHz. Datasheet doesn't give an explicit clock frequency min/max, but does have one AC timing ("MA[11:0] Flow Through Delay from HA for first read cycle") with a maximum of 12.8nS. And the SDRAM chip selects can take 6.3nS to become valid, with the RAM itself having some sort of setup and hold time. So I can see them guaranteeing 66MHz, but anything faster depends on how fast the particular chip is.

Out of interest, the WS48S84-4 datasheet gives two options for 75MHz, one with PCI at 32MHz (FS2:0=001, the only asynchronous one) and one at 37.5MHz (FS2:0=101). Do you know how yours was wired for 75?

The default wiring is for "1-0-1" with FS2 floating / internal pullup.
With FS2 pulled down - "0-0-1" - (asynch.) the northbridge needs even more cooling to start. I had expected the opposite, since I´m using a PCI videocard.
83 MHz will not start no matter how good the cooling might be. At 75 MHz this chip seems to operate at the edge.

If all else fails I´ll probably populate the FS2 pulldown resistor and live with a 68.5 FSB