BlackFX wrote on 2022-02-05, 04:56:
Hi all
I am looking for the bios for a Soyo 030f2, I have dumped the one in my board and the lower half is all FF which seems wrong to me 😀
Thanks
Hi BlackFX,
Here is a copy of the Soyo 030F2 REV. C2 BIOS.
- Filename
- Soyo-030f2-c2.zip
- File size
- 63.08 KiB
- Downloads
- 36 downloads
- File comment
- SY-030F2 Rev C2 BIOS original
- File license
- Public domain
I used this Soyo board myself when building my first 486 PC in 1995 and I used it until 2000. First I had an Am486 DX4-100 on it, but in 1997 I upgraded to an Am5x86-133 CPU.
But for the Am5x86 to run correctly, an updated BIOS is required.
I used this latest REV. C2 (11/24/94) BIOS to make a patched version for Am5x86-133 support.
I still have this patched 30F2 Rev C2 BIOS and it can be downloaded at:
http://www.steunebrink.info/bios/30f2-j2.zip
In the zip, you will find the BIOS image and a Changes.txt file that documents my patchwork in detail. 😉
This patched BIOS includes full Am5x86-133 support with L1 cache WB selection and x3/x4 mode support.
I've also fixed the 2 GB Harddisk Display limit bug, and the year 2094 bug in this patch J.2 BIOS.
Apart from these changes, I have enabled a lot of hidden BIOS features as well so that the chipset can be tweaked in more detail, depending on your configuration.
However, my experience was that when I selected LOAD SETUP DEFAULTS in the main BIOS menu, most BIOS options, especially the new ones, where already at their optimum value. 😉
I've sold this board in 2001, including the manual, but I've kept scans of some manual pages, the first 16 pages to be exact.
You can download the zipped 30F2 manual scans from:
http://www.steunebrink.info/Sy-30DEF.zip
You will notice that I scanned the 6 jumper settings pages in high resolution to improve readability. 😉
As the Am5x86-133 jumper settings are not in the manual, I used the Intel 486DX4-100 settings at page 13 with the following changes:
JP7: 2-3 (STPCLK# signal)
JP8: 2-3 (This pulls the CLKMUL pin low for 4x mode)
JP10: 1-2 (This pulls the WB/WT# pin high for L1 cache Write Back mode)
JP11: 1-2 (HITM# signal - for L1 cache WB mode)
Note also the correct JP21 settings for 5V or 3.3V CPUs!
With these settings and the patched C.2 BIOS, an Am5x86-133 should run correctly in 4 x 33 and L1 cache WB modes.
Note that the patched BIOS will indicate a DX4-S CPU, but this is just cosmetic. 😉
Jan
Edit: updated website links.
