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First post, by superfury

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When booting Linux Jessie on UniPCemu, it says that the APIC timer isn't working properly, thus reverting to using the two legacy PIC chips.

Does anyone know of diagnostic software that tests/diagnoses the APIC and IO APIC's functionality?

Last edited by superfury on 2022-01-13, 07:59. Edited 1 time in total.

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Reply 1 of 13, by superfury

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I'm just wondering now. What determines if the APIC timer is ticking and/or allowed to raise interrupts?
https://wiki.osdev.org/APIC_timer#Enabling_APIC_Timer

If that's to be believed, writing the divide configuration register or timer LVT stops the timer, while writing the
Then, looking at the Linux kernel's APIC code, it's even more weird.
https://github.com/torvalds/linux/blob/master … pic/apic.c#L333
It seems like the writing to the LVT stops the timer and writing the divide configuration register has no extra effect and writing the initial count register causes the timer to start. But the exception being when the timer is in periodic mode, where it starts once the LVT is written? Or perhaps it's started once the divide configuration register is written instead (since the linux kernel never writes the initial count in periodic mode)? So perhaps it's started by either divide configuration register or initial count in periodic mode, while only by the initial count in one shot mode?

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Reply 2 of 13, by superfury

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Hmmm... Debian Jessie says something strange at the start of it's boot process:

..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
APIC timer disabled due to verification failure
devtmpfs initialized
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Linux Jessie dmesg oldest entries scrolled back through the window
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So something isn't working somehow with the APIC timer?

Can anyone see what's going wrong? https://bitbucket.org/superfury/unipcemu/src/ … /hardware/pic.c

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Reply 3 of 13, by superfury

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Just improved the trigger mode/remote IRR bits to only be supported on the IO APIC and LINT0/LINT1 LVT registers. The others were handling those bits as well, but they shouldn't (for the other LVT registers). Also the LINT0/LINT1 registers when in level-sensitive mode weren't handling the Remote IRR case at all when in level-sensitive mode, which is now emulated.

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Reply 4 of 13, by superfury

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Hmmm... Although it's complaining about the APIC timer, I do see it throwing interrupt EFh timer interrupts while it's having bit 17 in the Timer LVT set (triggering various times, with IRQ0 from the IO APIC in between).
After that, it disables the timer by writing the LVT(300EFh), stops the counter(by writing 0).
After that, it's printing:

..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
APIC timer disabled due to verification failure

What does it mean, "verification failure"? I see it actually triggering interrupts while it's enabled (all interrupt EFh)? The IRQ0 handler from the PIT is actually triggering on interrupt 0x30, while the APIC timer is triggering interrupt 0xEF. Is there something wrong about that?

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Reply 5 of 13, by mr.cat

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Idk if it helps much but you could try using the kernel parameter "apic=debug", it should yield some more information. There's lot more of them listed in Documentation/kernel-parameters.txt.

Reply 6 of 13, by superfury

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mr.cat wrote on 2022-01-11, 19:47:

Idk if it helps much but you could try using the kernel parameter "apic=debug", it should yield some more information. There's lot more of them listed in Documentation/kernel-parameters.txt.

How do I pass that to the kernel when booting the installation cd-rom? I'm using the debian jessie i386-cd-1 iso from https://cdimage.debian.org/cdimage/archive/8. … .1/i386/iso-cd/ .

Hmmm... Goto help, then F5, then type install apic=verbose ?

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Reply 7 of 13, by mr.cat

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superfury wrote on 2022-01-11, 21:26:
mr.cat wrote on 2022-01-11, 19:47:

Idk if it helps much but you could try using the kernel parameter "apic=debug", it should yield some more information. There's lot more of them listed in Documentation/kernel-parameters.txt.

How do I pass that to the kernel when booting the installation cd-rom? I'm using the debian jessie i386-cd-1 iso from https://cdimage.debian.org/cdimage/archive/8. … .1/i386/iso-cd/ .

Hmmm... Goto help, then F5, then type install apic=verbose ?

Yeah I guess that works. Or you can press TAB in the main screen (or in the Advanced options screen) and enter the additional parameters there.

Reply 8 of 13, by superfury

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mr.cat wrote on 2022-01-11, 23:41:
superfury wrote on 2022-01-11, 21:26:
mr.cat wrote on 2022-01-11, 19:47:

Idk if it helps much but you could try using the kernel parameter "apic=debug", it should yield some more information. There's lot more of them listed in Documentation/kernel-parameters.txt.

How do I pass that to the kernel when booting the installation cd-rom? I'm using the debian jessie i386-cd-1 iso from https://cdimage.debian.org/cdimage/archive/8. … .1/i386/iso-cd/ .

Hmmm... Goto help, then F5, then type install apic=verbose ?

Yeah I guess that works. Or you can press TAB in the main screen (or in the Advanced options screen) and enter the additional parameters there.

It indeed shows the vmlinuz line. Do I need to add a space after "---" before "apic=verbose"?
Edit: It appears to be working ("--- apic=verbose").

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Reply 9 of 13, by superfury

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OK. With "--- apic=debug" I now get a whole lot more information:

1525-Linux_APIC_1.png
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Linux boot page 1
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1526-Linux_APIC_2.png
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Linux boot page 2
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Then the source code used for that version should be at https://github.com/torvalds/linux/blob/v3.16/ … nel/apic/apic.c .

So that Jiffies check at row 805 fails somehow?

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Reply 10 of 13, by superfury

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I'm just wondering.... Could it be that the issue is with the CMOS timer in this case? The CPU runs at roughly 10-20% realtime speed, while the CMOS updates it's time at 100% realtime speed (it's not in cycle-accurate mode, so it's updating at the same speed as a real one on the host machine).
So it's running at roughly 5-10 times the speed of all other hardware inside the emulated machine.

Could that be the cause of the issues with the APIC during Linux's boot?

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Reply 11 of 13, by superfury

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Hmmm.... With the CMOS in cycle-accurate mode (meaning that the clock ticks at emulated speed instead of realtime speed), it boots a bit further past the protection of the kernel text and data.
It starts some program or driver (a daemon as far as I can see) called system-udevd.

Then, pressing Ctrl-Break, it dumps out a whole stack trace of pretty much all processes:

1529-CtrlBreak output first interesting page_1.png
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Ctrl-Break's first interesting data. Some lock perhaps hanging?
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1530-CtrlBreak_anotherinterestingprogram_systemudevd_2.png
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Ctrl-Break's second interesting data. system_udevd
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1531-CtrlBreak_RunnableTasksListing_3.png
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1531-CtrlBreak_RunnableTasksListing_3.png
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Ctrl-Break's runnable task listing.
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Can you infer anything from that?

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Reply 12 of 13, by mr.cat

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Well well, so jessie is recent enough to have systemd...
The kernel got as far as trying to launch the first userland process (init, PID 1).
And systemd init then launches a whole bunch of daemons that are listed in your pic 1531.

In your first pic there's that __do_page_fault call in the trace (and handle_mm_fault as well).
But it not clear to me where exactly this was originated. If it's caused by systemd-udevd, adding the debug switch -D might help.
systemd-udevd is probably launched from lib/debian-installer/start-udev (that script resides inside of the initrd.gz image, might not be that simple to edit).

Do note that there are some distros without systemd such as Devuan and Void Linux for example.
But for UniPCemu Linux testing, alpine or Slackware are better alternatives than those two, because of the lack of an FPU.
The latest alpine versions (after 3.12) do require FPU by default though.

With alpine-extended-3.4.6-x86.iso the boot actually gets pretty far, but eventually drops into an emergency shell.
The other alpine versions barf various errors (something like "Fatal exception in interrupt").

Reply 13 of 13, by superfury

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Hmmm... Does anyone know exactly when a command register keeps pending without erroring out? Say you send an interrupt to an CPU that's already having the interrupt (it's IRR) pending for said interrupt vector. What happens in that case? Does it keep pending until it's fired (transfers to ISR) or does it fail on the sender's side?

Also, does the interrupt flag affect the IVT registers and IRR register the same as with the 8259(A) PIC?

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