LocalBus wrote on 2022-02-09, 11:30:

So from where would the 82C822 get LCLK (pin 82) and CLK (pin 80) ? Definitely synchronous mode then, just need to find the CLK source for the same:

Haven't tracked it all, but it looks like the 822 pin 82 comes from the PCI clock, from the R40 output from the clock buffer.

snufkin wrote on 2022-02-09, 13:04:

LocalBus wrote on 2022-02-09, 11:30:

So from where would the 82C822 get LCLK (pin 82) and CLK (pin 80) ? Definitely synchronous mode then, just need to find the CLK source for the same:

Haven't tracked it all, but it looks like the 822 pin 82 comes from the PCI clock, from the R40 output from the clock buffer.

Confirmed, I will provide a more thorough update later - but yes - R40 goes to pin 80 and pin 82 on the 82C822.

More importantly, its clock source is copied all the way from [SN74ABT245] pin 13 (B6) via JP13 to pin 2, 3, 4 and 5 (A1, A2, A3 and A4) via R38. Pin 7 (A6) is copied from B5, which gets its clock from A5 input - yep - Chrontel 9007E main CLK pin 11 (via R32).

The other position of JP13 would use the external oscillatoras clock source for the PCI bus (and I guess also VL Chipset / VL Bus clock).

So we are feeding 66 MHz to the PCI bus and the 82C822 😀

snufkin wrote on 2022-02-09, 12:45:

Interesting idea. Looking back, I think the main Chrontel output is duplicated, with one branch going somewhere under the 571. […]
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Interesting idea. Looking back, I think the main Chrontel output is duplicated, with one branch going somewhere under the 571. The other branch goes to JP13, along with (probably) the output from the oscillator, JP13 selects which drives the middle pin. That middle pin directly drives the 572, and has two copies made, one which goes under the 571 and the other toward the Socket 4 (and I assume it then goes on the Socket 5). So the Chrontel seems to always drive the 571, and everything else can switch between the external oscillator or the Chrontel. I don't know where the PCI clock comes in from, but that has 4 copies made that go up to the slots.

Could try slowing the chrontel down. I never did find a 9007 datasheet. But the frequency outputs in that paper I found for the 9007 match the frequencies for the 9008D. So it's possible that the 9007E matches the 9008E. In which case it looks like JP28 is Fs0 (1-2), FS1 (3-4), FS2 (5-6), SD (7-8). The Slow Down (SD) input selects a slower speed when it is pulled low. All the inputs have internal pull ups, so I assume the jumper pull the line low when fitted. So the frequency table would be:

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1012S
2.... 50 / 8
3|... 80 / 16
4.|.. 60 / 16
5||.. 66 / 16
6..|. 50 / 16
7|.|. 40 / 8
8.||. 33 / 8
9|||. 25 / 8

I don't know how low your CPU will clock, but maybe try 1-2,5-6 to select 40MHz?

[a datasheet for some Pentium processors suggests that the bus speed can go down to half. So, e.g., I think a P90 expecting a 60MHz bus should work as a P45 on a 30MHz bus.]

I will definitely try a lower CPU clock and see if this takes us any further.

DIL-14 33.333 MHz oscillators are basically unobtainium right now, but maybe I could wire a SMD HCMOS one instead - modding 14 pin socket or similar.

I am not surprised that the oscillator was missing from the board, it barely stays in the milled / round hole socket - would need a cable-tie to hold it in place during transport.

Would any of these fit the bill? Or it must be TTL?

https://www.mouser.se/c/passive-components/fr … 20voltage=5%20V

Hell yes!! It likes 40 MHz PCI / VLB clock better 😉

All this time, just in front of us... oh well, too early to celebrate! Next up, graphics card!

Ok, I'm grabbing a beer 🍺

This calls for celebration!! Ladies and gentlemen, we got a POST video output:

I can't thank you all enough for hanging in there and supporting me! We sure got stuck on the 82C206 there for a while!! @rasz_pl's custom BIOS finally got me off the hook, the RTC was working just fine 🙂 @snufkin @Chkcpu @rasz_pl @maxtherabbit @BitWrangler@pentiumspeed @stamasd @cyclone3d ... well all of you! THANKS!! 😊

Yay!

Damnit. I knew I hadn't traced where those PCI clock outputs from the buffer got their source from, I just assumed it'd be 1/2 the clock, possibly handled by that 74f74.
[and I was definitely pushing the faulty 206 theory, even after rasz_pl pointed out that the CMOS bit must have been working]

Still, couple of other faults fixed along the way.

So, why JP13? Does it only need the external clock when using a Pentium, and for a 486 it can just use the Chrontel?

Now you just need to work out what all the jumpers do. After the beer. Best time to do that.

snufkin wrote on 2022-02-09, 17:53:

Yay! […]
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Yay!

Damnit. I knew I hadn't traced where those PCI clock outputs from the buffer got their source from, I just assumed it'd be 1/2 the clock, possibly handled by that 74f74.
[and I was definitely pushing the faulty 206 theory, even after rasz_pl pointed out that the CMOS bit must have been working]

Still, couple of other faults fixed along the way.

So, why JP13? Does it only need the external clock when using a Pentium, and for a 486 it can just use the Chrontel?

Now you just need to work out what all the jumpers do. After the beer. Best time to do that.

Yay indeed!

It was definitely worth the walkthrough, not only did we fix some various flaws along the way - I did also learn a ton of stuff!

"So, why JP13?" Yes I think the design is as you say - a hybrid 486/Pentium board - and with a 486 with 33 Mhz / 40 Mhz FSB, then the VLB (and PCI) can run at the same clock. With a Pentium with 60 / 66 MHz FSB - not so much. Now I can understand why the 486 DX50 is such a unicorn.

Yes work out jumpers, recap, change BJTs, put the battery back on...

Any suggestion of a replacement oscillator that is actually obtainable? Would any "modern" SMD oscillators work? TTL ones are hard to find, but there are those that handles 5V supply voltage, but is CMOS drive...

https://www.ebay.ca/itm/185159751786?hash=ite … b0AAOSw7mJZ1Uqe

What about this?

These SMD small ones are 3.3V, so not compatible.

Cheers,

pentiumspeed wrote on 2022-02-09, 18:11:

https://www.ebay.ca/itm/185159751786?hash=ite … b0AAOSw7mJZ1Uqe […]
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https://www.ebay.ca/itm/185159751786?hash=ite … b0AAOSw7mJZ1Uqe

What about this?

These SMD small ones are 3.3V, so not compatible.

Cheers,

Cheers! I will place an order on one of these asap!

Soon I will have a spare UM82C206F, but I shouldn't jinx it - there are several miles to go with IRQ and DMA before I can rule out the one I have 😀

CMOS->TTL should be fine. 5V CMOS low output is <0.2V and high output is >4.7V. For TTL a low input must be <0.8V and high input >2.0V. So anything TTL will see CMOS outputs as good highs or lows. Going the other way (TTL in to CMOS) might be a problem, but that doesn't matter for the clock. Double check the Vdd pin for the oscillator.

There are some 5V surface mount oscillators (e.g. https://docs.rs-online.com/8c71/0900766b8167459f.pdf), but a plug in one like the one suggested will just be easier. Not uncommon to see a zip tie holding the crystal in the socket.

[edit: depending on where you are, shipping and so on, there's also this: https://www.ebay.co.uk/itm/153450737245 ]

[forgot to say: Doornkaat wins the prize:

Doornkaat wrote on 2021-11-27, 19:24:

That's very cool!
Could the missing oscillator be the culprit?

]

snufkin wrote on 2022-02-09, 18:29:

CMOS->TTL should be fine. 5V CMOS low output is <0.2V and high output is >4.7V. For TTL a low input must be <0.8V and high input >2.0V. So anything TTL will see CMOS outputs as good highs or lows.

Depends. There is also the CMOS sink current to consider. For gates like LSTTL it may be enough, but for more power-hungry TTL families like S or F it may not. Especially for older CMOS families like the CD4000.

snufkin wrote on 2022-02-09, 18:29:

CMOS->TTL should be fine. 5V CMOS low output is <0.2V and high output is >4.7V. For TTL a low input must be <0.8V and high input >2.0V. So anything TTL will see CMOS outputs as good highs or lows. Going the other way (TTL in to CMOS) might be a problem, but that doesn't matter for the clock. Double check the Vdd pin for the oscillator.

There are some 5V surface mount oscillators (e.g. https://docs.rs-online.com/8c71/0900766b8167459f.pdf), but a plug in one like the one suggested will just be easier. Not uncommon to see a zip tie holding the crystal in the socket.

[edit: depending on where you are, shipping and so on, there's also this: https://www.ebay.co.uk/itm/153450737245 ]

Thanks! Already pulled the trigger on the other one, located in Sweden - but I would say the shipping time these days (and with customs handling) - it is about the same 😉

🎉 🍰 I learned a ton just reading thru awesome Chkcpu disassembly listing and fixing broken IDA disassembly one step at a time. IDA failed to recognize jump table and loading rom offsets into SP to simulate stack as a valid return address

1mov     sp, offset off_F01E4
2jmp     ret_sub_1
3off_F01E4       dw offset loc_F01E6
4loc_F01E6:

This trick is simulating fixed stack without initialized ram and lets one call procedures. BIOS_Disassembly_Ninjutsu_Uncovered talks about IDA plugins, maybe they are required for full proper disassembly with IDA. Chkcpu mentioned Sourcer, looks like that was THE program for RE back in the nineties https://corexor.wordpress.com/2015/12/09/sour … windows-source/
"V Communication has been marketing this product using one of customer testimony that disassembly listing provided by Sourcer is actually more clean than the source code provided by BIOS manufacturer."
Sourcer author Frank van Gilluwe even wrote a book 'The Undocumented PC' https://archive.org/details/The_Undocumented_ … rankvan_Gilluwe https://www.pcjs.org/software/pcx86/sw/books/ … ndocumented_pc/ There goes my weekend 😀

LocalBus wrote on 2022-02-09, 17:38:

Ok, I'm grabbing a beer 🍺 […]
Show full quote

Ok, I'm grabbing a beer 🍺

This calls for celebration!! Ladies and gentlemen, we got a POST video output:

20220209_183553.jpg

I can't thank you all enough for hanging in there and supporting me! We sure got stuck on the 82C206 there for a while!! @rasz_pl's custom BIOS finally got me off the hook, the RTC was working just fine 🙂 @snufkin @Chkcpu @rasz_pl @maxtherabbit @BitWrangler@pentiumspeed @stamasd ... well all of you! THANKS!! 😊

@ LocalBus Great you got the board to POST!! 😀

Jan

rasz_pl wrote on 2022-02-09, 20:23:

:tada: :cake: I learned a ton just reading thru awesome Chkcpu disassembly listing and fixing broken IDA disassembly one step at […]
Show full quote

🎉 🍰 I learned a ton just reading thru awesome Chkcpu disassembly listing and fixing broken IDA disassembly one step at a time. IDA failed to recognize jump table and loading rom offsets into SP to simulate stack as a valid return address

Copy code to clipboard

1mov     sp, offset off_F01E4
2jmp     ret_sub_1
3off_F01E4       dw offset loc_F01E6
4loc_F01E6:

This trick is simulating fixed stack without initialized ram and lets one call procedures. BIOS_Disassembly_Ninjutsu_Uncovered talks about IDA plugins, maybe they are required for full proper disassembly with IDA. Chkcpu mentioned Sourcer, looks like that was THE program for RE back in the nineties https://corexor.wordpress.com/2015/12/09/sour … windows-source/
"V Communication has been marketing this product using one of customer testimony that disassembly listing provided by Sourcer is actually more clean than the source code provided by BIOS manufacturer."
Sourcer author Frank van Gilluwe even wrote a book 'The Undocumented PC' https://archive.org/details/The_Undocumented_ … rankvan_Gilluwe https://www.pcjs.org/software/pcx86/sw/books/ … ndocumented_pc/ There goes my weekend 😀

@rasz_pl
Okay, you discovered the "ROM_call" trick as well. 😉
That book "The Undocumented PC" Second Edition is my favorite PC hardware book. I still take it down from my bookshelf regulary to look something up.

Using the POST card as Hex display through that BIOS hack was a brilliant idea, when faced with a hang before the video is initialized!

Have a nice weekend,
Jan

Started sketching the layout:

Not all labelled. I've noted pin 1 with a dot where I'm fairly sure.

Also jotted down some jumpers based on having a quick read back through the thread (haven't noted the detailed settings yet).

1JP21 - External battery (1 +ve, 4 -ve?)
2JP24 - CMOS clear (1-2 clear, 2-3 normal?)
3JP11 - BIOS programming voltage 12V/5V (1-2 5V, 2-3 12V)
4JP33 - CPU multiplier? (silkscreen says to fit jumpers for P60/66, remove for P90/100?  Or voltage select, seems to be power related?)
5JP28 - CPU FSB frequency
6JP13 - Bus clock source (FSB or oscillator)
7JP10 - Speaker
8JP22 - Keylock
9
10JP26 }
11JP27 } Turbo switch/LED + Reset?
12JP18 }
13
14JP23 - near KBC
15
16JP12 }
17JP15 } near BIOS
18JP5  } (JP5 something to do with resistor configuration, could be voltage adjust?)
19
20JP1  }
21JP2  } near Clock Gen - go to BF pins on Socket 5, so CPU multiplier?
22JP3  }
23JP29 (Not fitted)
24
25JP32 }
26JP34 } near 82C822
27
28JP17 }
29JP19 } near 82C572
30JP16 }
31
32JP8  }
33JP?? } near cache
34
35missing 4,6,7,9,14,20,25,30,31 (one of these will be the one near JP8)

Awesome! Glad you got it working.

cyclone3d wrote on 2022-02-10, 04:45:

Awesome! Glad you got it working.

Thanks! All the troubleshooting makes it all so much more worth now! 😀

snufkin wrote on 2022-02-10, 01:55:

Started sketching the layout: PCI560_Layout.png […]
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Started sketching the layout:
PCI560_Layout.png

Not all labelled. I've noted pin 1 with a dot where I'm fairly sure.

Also jotted down some jumpers based on having a quick read back through the thread (haven't noted the detailed settings yet).

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1JP21 - External battery (1 +ve, 4 -ve?)
2JP24 - CMOS clear (1-2 clear, 2-3 normal?)
3JP11 - BIOS programming voltage 12V/5V (1-2 5V, 2-3 12V)
4JP33 - CPU multiplier? (silkscreen says to fit jumpers for P60/66, remove for P90/100?  Or voltage select, seems to be power related?)
5JP28 - CPU FSB frequency
6JP13 - Bus clock source (FSB or oscillator)
7JP10 - Speaker
8JP22 - Keylock
9
10JP26 }
11JP27 } Turbo switch/LED + Reset?
12JP18 }
13
14JP23 - near KBC
15
16JP12 }
17JP15 } near BIOS
18JP5  } (JP5 something to do with resistor configuration, could be voltage adjust?)
19
20JP1  }
21JP2  } near Clock Gen - go to BF pins on Socket 5, so CPU multiplier?
22JP3  }
23JP29 (Not fitted)
24
25JP32 }
26JP34 } near 82C822
27
28JP17 }
29JP19 } near 82C572
30JP16 }
31
32JP8  }
33JP?? } near cache
34
35missing 4,6,7,9,14,20,25,30,31 (one of these will be the one near JP8)

Brilliant, filling in with some of the blanks I have "figured out":

1JP21 - External battery (1 +ve, 4 -ve?) [b]-> Will measure this[/b]
2JP24 - CMOS clear (1-2 clear, 2-3 normal?) [b]-> Correct[/b]
3JP11 - BIOS programming voltage 12V/5V (1-2 5V, 2-3 12V)
4JP33 - CPU multiplier? (silkscreen says to fit jumpers for P60/66, remove for P90/100?  Or voltage select, seems to be power related?) [b]-> Enabling 5V power to Socket 4 as well as disabling 3.3V voltage regulator. Technically only one of these jumpers needs to be shorted, but maybe need to carry a lot of current and thus need both JP33 populated. [/b]
5JP28 - CPU FSB frequency
6JP13 - Bus clock source (FSB or oscillator)
7JP10 - Speaker
8JP22 - Keylock
9
10JP26 } [b]-> Turbo LED[/b]
11JP27 } Turbo switch/LED + Reset? [b]-> Turbo Switch[/b]
12JP18 } [b]-> Reset Switch[/b]
13
14JP23 - near KBC [b]-> This jumper shorts KBC pin-33 to GND (depending on KBC I guess?)[/b]
15
16JP12 }
17JP15 } near BIOS [b]-> both JP12 and JP15 are related to how adress / data lines are routed to the BIOS ROM chip. Removing JP12 makes no difference, but shorting JP15 is no POST (will probe this)[/b]
18JP5  } (JP5 something to do with resistor configuration, could be voltage adjust?) [b]-> Yes voltage setting, position 2-3 gives 3.3V, position 1-2 gives 3.6V[/b]
19
20JP1  }
21JP2  } near Clock Gen - go to BF pins on Socket 5, so CPU multiplier? [b]-> Yes multiplier setting, I traced these to the Socket 5 (BF0, BF1, BF2).[/b]
22JP3  }
23JP29 (Not fitted)
24
25JP32 } [b]-> JP32: 82C822 pin 104 NMIIN (Non-maskable Interrupt Input) - no jumper right now - goes straight to NMI on CPU (trace goes to Socket 4/5, have not checked which pin) [/b]
26JP34 } near 82C822 [b]-> JP34: 82C822 pin 125 LRDY# -> 82C822 pin 131 BRDY#[/b]
27
28JP17 }
29JP19 } near 82C572 [b]-> Memory itentification / configuration? Each jumper connects to a pull-down resistor 1kOhm. Goes to 82C572 but also to disapperas underneath the top-most SIMM (Bank3) [/b]
30JP16 } 
31[b]82C572 pin 149 -> R53 -> JP17 -> GND
32
3382C572 pin 152 -> R52 -> JP19 -> GND (current jumper position)
34
3582C572 pin 153 -> R51 -> JP16 -> GND[/b]
36
37JP8  }
38JP9 } near cache [b]-> Probably cache size settings?[/b]
39
40missing 4,6,7,9,14,20,25,30,31 (one of these will be the one near JP8)

I can report that the memory configuration is not super straight forward with this chipset. I have 4 pcs of 8MB (dual sided) 60ns FPM modules at disposal, putting these in Bank0, Bank1 and Bank2 works fine for a total of 24 MB. However, populating Bank3 as well and I get a POST code suggesting problem with memory detection.

Consulting this manual (with corresponding chipset), I found that in order to reach say a total of 32 MB, you need to either go 2x 16MB modules (Bank0 + Bank2 or Bank0 + Bank1), or just 1x 32MB module in Bank0) ->

https://www.ultimateretro.net/en/motherboards/4989#downloads
https://www.ultimateretro.net/motherboard/manual/32694.pdf