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Compaq Proliant 1500 No Post -Reset line being held high

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First post, by scruit

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Hello all,

Still occasionally breaking out the Compaq Proliant that won't POST, and mapping out the board looking for a reason.

History: Proliant 1500 Dual P166. On power up there is no sync to the VGA, no post, POSTCard shows nothing at all ("-- --"). The ISA address/data lines show a burst of activity for around 10-20 seconds before ceasing. Clock lines looks goos to a certain extent... Some things get the expected clock signals and some don't. BIOS Rom, specifically, gets not clock/data/address acticvity. Even with the ROM removed, there is no activity so it's not a shorted ROM pulling the clock/address/data low.

Current testing: I am testing the EISA chip, and the PCI-EISA bridge associated with it. These get the expected clock signal IN but are not producing the expected clock signals out (one pin goes direct to the BIOS ROM).

Then I noticed the reset line is being held high all the time. Oscilloscope trace shows that the reset line goes low when the system is powered off, and on powerup it goes high and stays there. This does not appear to be a reset-on-low signal like a C64 or similar. The EISA chip datasheet says "When asserted" the chip going to reset state until rest i no longer "asserted".

So my next steps are to understand what is driving the rest line high. I already tested the power-good line from the PSU so I know the PSU is trying to start the board.

Anyone got any experience / ideas / links that would help me understand the sequence of events that a pentium motherboard would go through before choosing to drop the reset line and let the system boot up?

Reply 1 of 2, by mkarcher

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scruit wrote on 2022-05-01, 14:12:

Then I noticed the reset line is being held high all the time. Oscilloscope trace shows that the reset line goes low when the system is powered off, and on powerup it goes high and stays there. This does not appear to be a reset-on-low signal like a C64 or similar. The EISA chip datasheet says "When asserted" the chip going to reset state until rest i no longer "asserted".

Be careful and double-check your understanding of the documentation. "asserted" and "not asserted" does not necessarily mean "high" and "low" in this order, but merely "asserted"="the level that means something" and "deasserted" = "the level that means nothing". On your C64, in that case, the reset line is "active low", so "asserted" means "low" and "deasserted" means high. These terms are used to describe the meaning of the level without caring about the hardware implementation.

Typical indicators for a signal being active low are:

  • The signal is described as "active low"
  • The signal name is written with a line above the name
  • The signal name starts with a slash, as in /RESET. Actually, the slash is a hint for the line above that isn't representable in plain ASCII text.
  • The signal name ends in a hash/pound/octothorpe/number sign character, as in RESET#

I know for sure, that the RESET pin on the ISA bus (B2) is active high, so if you measured that pin, you are correct with your diagnosis that something keeps the machine in permanent reset. If you measure some signal going into the EISA bridge on the other hand, chances are quite high that it is active low just like on the C64.

Reply 2 of 2, by scruit

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mkarcher wrote on 2022-05-01, 16:51:

The signal name ends in a hash/pound/octothorpe/number sign character, as in RESET#

Oh wow... You just save me a TON of wasted time. I assumed that adding a leading "/" or putting a line above the pin name were the alternate ways to denote active-low. I didn't know that the trailing "#" also meant that.

I double-checked the datasheets for the 82374 EISA controller and the 82375 PCI-EISA bridge, and the pins are labeled "95: RESET#" and "93: PCIRST#" respectively.

So the "reset" direction would have been a wild goose chase. I'll double-check the reset line at pin B.02 on the ISA slot to be sure, but I have no doubt you are absolutely correct.

Thank you!

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