As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this patched M912 BIOS public.

@weedeewee, thanks for this first test! I’m glad that the different cache sizes are now indicated correctly. 😀

Here is the DX-6900/M912 VER 2.21r Award BIOS with patch J.1.
Apart from correcting the fake 256K Cache Memory display, this patch J.1 BIOS it identical to the original 09/08/95-UMC-498GP-2C4X6B13-00 VER 2.21r BIOS.
I’m now working on a patch J.2 version to add full Am5x86-P75 support.

Jan

Chkcpu wrote on 2022-01-17, 20:35:

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this pat […]
Show full quote

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this patched M912 BIOS public.

@weedeewee, thanks for this first test! I’m glad that the different cache sizes are now indicated correctly. 😀

Here is the DX-6900/M912 VER 2.21r Award BIOS with patch J.1.
Apart from correcting the fake 256K Cache Memory display, this patch J.1 BIOS it identical to the original 09/08/95-UMC-498GP-2C4X6B13-00 VER 2.21r BIOS.
I’m now working on a patch J.2 version to add full Am5x86-P75 support.

Jan

Going to try it soon.
Can we ask for other modifications? Like HD size?

Chkcpu wrote on 2022-01-17, 20:35:

I’m now working on a patch J.2 version to add full Am5x86-P75 support.

Amazing!

Nexxen wrote on 2022-01-18, 10:02:

Can we ask for other modifications? Like HD size?

Hi Nexxen,

You can always ask but no, I never modified a BIOS to break the 8GB HDD barrier.
As you probably know, such a mod would involve adding the IBM/Microsoft Int 13h extensions to the Int 13h interface. As the BIOS Interrupt 13h handler is already a very complicated piece of code, I always considered such a mod way beyond my expertise.

Luckily we have XTIDE now to get around the 8 GB limit on 486 systems when using IDE, but you need to have the XTIDE BIOS loaded on an (E)EPROM plugged into a supporting ISA network card or XTIDE ISA ROM card. But a cleaner approach would be to have this fixed in the MB's BIOS and this is the solution where I’m looking at. It would also free an ISA slot.

feipoa, the OP of this thread, pitched me this idea but it is still early days and I’m just beginning to understand what’s involved to make it work.
One obvious hurdle is BIOS ROM size. Any ISA/VLB 64KB BIOS often has less than a 100 bytes of free space and is simply too small to house XTIDE. So we need a 128KB BIOS as found on 486 PCI and early socket 5 boards. I’ve started looking at uncompressed Award v4.50G BIOSes with 32KB free space or more as a first step.

Yes, I got myself a nice winter project. 😉
Jan

Chkcpu wrote on 2022-01-14, 20:42:

On request of another M912 user, I made a detailed analysis of the 10/05/94 and 11/03/94 Award BIOSes for this board back in 201 […]
Show full quote

On request of another M912 user, I made a detailed analysis of the 10/05/94 and 11/03/94 Award BIOSes for this board back in 2019, to see if patching for Am5x86-P75 was possible.
So I’m joining here to share my findings.

The differences I found were:
- The 10/05/94 BIOS supports 2 IDE drives (only the Primary IDE channel), while the 11/03/94 BIOS supports 4 drives (Primary and Secondary IDE channel)
- The 11/03/94 BIOS adds support for the Am486DX4 (non-WB) CPU, so the 10/05/94 doesn’t and will indicate an Am486DX4 as an 80486DX2.
So only 2 small differences, which is to be expected in view of the 1 month difference in compilation date.

When looking at missing support and bugs in both these BIOSes, there are quite some similarities:
- Year 2094 bug
- 2GB HDD display limit bug
- No support for Enhanced Am486DX2/DX4, Am5x86, and Cyrix 5x86 CPUs.
- No x4 multiplier or L1 cache WB support for these later CPU models. L1 cache WB is only supported for Intel P24D, P24T, and Cyrix 486 models.

As the 11/03/94--2C4X6H01-00 BIOS is the latest Award BIOS from PCChips, many M912 users turn to the AMI 12/02/1995X BIOS when running an Am5x86-P75.

Recently I have been looking at the Award BIOS for the Amptron DX-6900, an M912 clone. However this 09/08/95-UMC-498GP-2C4X6B13-00 BIOS is indicated for the v1.4 board only. See https://www.ultimateretro.net/nl/motherboards/6821
This 09/08/95 BIOS is free from the above bugs and supports all later 486 models, except the Am5x86 in x4 multiplier mode. However, this can be patched. 😉

Did any of you try this BIOS on a DX-6900/M912 v1.7?

Cheers, Jan

Would it be possible to do the same with the AMI Bioses, the original 12/01/1995 and the weird 12/02/1995X which no1 knows where it came from?

Am386DX-40 wrote on 2022-01-31, 14:32:

Would it be possible to do the same with the AMI Bioses, the original 12/01/1995 and the weird 12/02/1995X which no1 knows where it came from?

Hi Am386DX-40,

Alas, I have little experience with the AMI BIOS. I did a few AMI socket 7 BIOS patches for K6plus support and once I disassembled an 011094 AMI 486 BIOS for the Addtech 4GLX3. But the AMI WinBIOS is still a mystery to me. 😉

So I’m unable to tell you anything about these M912 AMI BIOSes, but when the Award patch J.2 BIOS for this board is ready, I hope it will be a good alternative for the AMI 12/02/1995X!

Jan

Nexxen wrote on 2022-01-18, 10:02:

Chkcpu wrote on 2022-01-17, 20:35:

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this pat […]
Show full quote

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this patched M912 BIOS public.

@weedeewee, thanks for this first test! I’m glad that the different cache sizes are now indicated correctly. :)

Here is the DX-6900/M912 VER 2.21r Award BIOS with patch J.1.
Apart from correcting the fake 256K Cache Memory display, this patch J.1 BIOS it identical to the original 09/08/95-UMC-498GP-2C4X6B13-00 VER 2.21r BIOS.
I’m now working on a patch J.2 version to add full Am5x86-P75 support.

Jan

Going to try it soon.
Can we ask for other modifications? Like HD size?

Nexen, how did the BIOS workout?

feipoa wrote on 2022-02-11, 20:42:

Nexxen wrote on 2022-01-18, 10:02:

Chkcpu wrote on 2022-01-17, 20:35:

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this pat […]
Show full quote

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this patched M912 BIOS public.

@weedeewee, thanks for this first test! I’m glad that the different cache sizes are now indicated correctly. 😀

Here is the DX-6900/M912 VER 2.21r Award BIOS with patch J.1.
Apart from correcting the fake 256K Cache Memory display, this patch J.1 BIOS it identical to the original 09/08/95-UMC-498GP-2C4X6B13-00 VER 2.21r BIOS.
I’m now working on a patch J.2 version to add full Am5x86-P75 support.

Jan

Going to try it soon.
Can we ask for other modifications? Like HD size?

Nexen, how did the BIOS workout?

I also tried the bios and can only say, it works. it now reports the correct cache size. other noticeable thing is the selection for four hdds in stead of the usual two with those old boards.

feipoa wrote on 2022-02-11, 20:42:

Nexxen wrote on 2022-01-18, 10:02:

Chkcpu wrote on 2022-01-17, 20:35:

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this pat […]
Show full quote

As this was the first time I did a patch to correct a fake cache BIOS, I requested one member to test it, before making this patched M912 BIOS public.

@weedeewee, thanks for this first test! I’m glad that the different cache sizes are now indicated correctly. 😀

Here is the DX-6900/M912 VER 2.21r Award BIOS with patch J.1.
Apart from correcting the fake 256K Cache Memory display, this patch J.1 BIOS it identical to the original 09/08/95-UMC-498GP-2C4X6B13-00 VER 2.21r BIOS.
I’m now working on a patch J.2 version to add full Am5x86-P75 support.

Jan

Going to try it soon.
Can we ask for other modifications? Like HD size?

Nexen, how did the BIOS workout?

Didn't have the time.
Had issues with neighbors and it's not going well.

I'll try next week. Weedeewee has the answer though, and I trust the guy.

OK thanks.

Nexxen wrote on 2022-02-11, 22:28:

Had issues with neighbors and it's not going well.

Tell me about it!

I once had this issue with my west-side neighbour because he was excavating his backyard to lower the water table. My yard was up about 1 metre higher than his. So he starts digging up all my fence posts, although my fence is just inside my property boundary. I confronted him about it and I was told that I should have put the fence deeper inside my property line to avoid this issue. LOL! Ultimately, their decision cost me out of pocket - I had to build a 1 m tall concrete retaining wall to hold in my yard, while preventing it from spilling onto theirs. The fence then was saddled over the concrete wall. Neighbour wouldn't pay for the concrete retaining wall and didn't want the wall over their property line.

I had other issues with north-east side neighbours about some tall fir trees on our lot. Neighbour was afraid they were going to fall on their house in a wind storm. Long story short, I ultimately had to pay for the trees to be removed and pay the several thousand dollars in fines to remove "protected trees".

A different neighbour, north-west side this time, then complained about me removing some other protected trees without a permit on the other end of the property, and I had to pay more several thousands in fines.

The moral I learned for these experiences were: just because you are a property owner, doesn't mean you own the property.

feipoa wrote on 2022-02-12, 00:12:

OK thanks. […]
Show full quote

OK thanks.

Nexxen wrote on 2022-02-11, 22:28:

Had issues with neighbors and it's not going well.

Tell me about it!

I once had this issue with my west-side neighbour because he was excavating his backyard to lower the water table. My yard was up about 1 metre higher than his. So he starts digging up all my fence posts, although my fence is just inside my property boundary. I confronted him about it and I was told that I should have put the fence deeper inside my property line to avoid this issue. 🤣! Ultimately, their decision cost me out of pocket - I had to build a 1 m tall concrete retaining wall to hold in my yard, while preventing it from spilling onto theirs. The fence then was saddled over the concrete wall. Neighbour wouldn't pay for the concrete retaining wall and didn't want the wall over their property line.

I had other issues with north-east side neighbours about some tall fir trees on our lot. Neighbour was afraid they were going to fall on their house in a wind storm. Long story short, I ultimately had to pay for the trees to be removed and pay the several thousand dollars in fines to remove "protected trees".

A different neighbour, north-west side this time, then complained about me removing some other protected trees without a permit on the other end of the property, and I had to pay more several thousands in fines.

The moral I learned for these experiences were: just because you are a property owner, doesn't mean you own the property.

You have non cooperative neighbors, the worst kind. Some people really think they are entitled to anything.

I live in a flat, the upper guys make noise whenever they feel like.
Wife wakes up at 5-5.30 am and start cleaning around 6, stops at 9-ish. Noise like if it was noon. But keeps going all day moving stuff, cleaning and repeat.
And they say I have issues 😀 She has severe depression issues and it's death, you just can't talk with her.
Husband defends her but it's so blatant they are at fault even other neighbors feel sorry for me.

I wouldn't give two hoots about it during daytime, but she wakes me up and even when I sleep at night she makes noise before bed...
I had to go sleep at my parents more than once to have some rest and good uninterrupted sleep. And before that at my gf's place.

I think I'm going to test this bios next week.

Ahh, flat life. I don't miss it. Next time you are looking for a unit to rent, try to get the top floor! That had always been my strategy and it worked well for me.

feipoa wrote on 2022-02-13, 01:48:

Ahh, flat life. I don't miss it. Next time you are looking for a unit to rent, try to get the top floor! That had always been my strategy and it worked well for me.

Rant mode on
I'm the owner (weeping sound). Before lockdown they were crazy but acceptable. After, the wife became aggressive and confrontational, even worse than before.
I can't cross her without getting insulted. The husband is non existent as a balancing force, just an accessory walking like a ghost. Never saying hello.
They make a point saying they are good christians but when they have fights what they say to each other isn't christian at all.
Rant mode off.

I'm happy that more people are getting interested in modding BIOS.
I have to try modbin myself to see if it does anything. A few stripped down bioses could really benefit.

Nexxen, it sounds like the wife may be going through perimenopause. I've had first hand, 3rd person observational experience with this. Changing hormones can turn those who are otherwise pleasant into monsters, and unfortunately, the monster isn't able to see themselves.

Update: I have received Jan's updated BIOS and will be setting up a testbed this evening. I have both v1.4 and v1.7 of this motherboard. Are there any particular deliverables other than these:

a) Am5x86 & Cx5x86 4x mode check;
b) Am5x86 & Cx5x86 WT & WB mode check;
c) 8 GB HDD check, presumabley on a VLB IDE card;
d) ensure 256, 512, and 1024K L2 cache are correctly displayed and usable via cachechk?

Any possibility to increase the HDD detection limit to 32 GB?

I'll be using a Holtek HT6560A w/HT6550 & HT6570 for the multi I/O VLB card, unless anyone thinks a Winbond W83759F w/W83757F & W83758P is preferable. I also plan to use a Trio64 VLB card with an 8 GB compact flash IDE card.

Any news on VER 2.21r J2 version and adding full 5x86 support?

I managed to get DualBIOS feature to work on this mobo (v1.4). TLDR: I used Intel's 28F020, 29-series chip doesn't work with AMI. Will test UV EPROM soon.
EDIT: yep, good old 27c010 works just fine for DualBIOS. Also AWARD and AMI store their settings differently so you'll have to reset them every time you change the BIOS.
For this to work you will have to desolder the original chip and solder DIP32 socket instead. The original chip is most likely 27C512 (512kbit) which is DIP28, however DualBIOS requires twice as much capacity, and the board supports such chips.
What did I do:
1. I joined M912_12-02-1995X.bin (AMI) with R221R_J1.BIN (AWARD, modded by Chkcpu) with HxD hex editor. The resulting file is AMI + AWARD and is 1mbit in size.
2. Flashed it into SST 29EE010 1mbit EEPROM. It DID NOT work! Only AWARD was booting, AMI was getting stuck at a certain post code. The specific BIOS is chosen by JP2 on the board, and all this does is ties A16 either to +5V or to GND, thus either selecting upper or lower part of the ROM chip, i.e. either AMI or AWARD.
3. I wtf-ed at the board because it had to work. I always presumed 29 EEPROMs was completely backwards-compatible with 27 ROMs. However I remember Intel's 28F020 datasheet mentioning something about compatibility with old-style ROMs. So I took Intel 28F020 FlashROM (two times bigger than we need, but I don't have any 28F010s). I joined my combo BIOS file with itself, so the content is repeated. The resulting BIOS image looks like this: AMI+AWARD+AMI+AWARD, and is 2mbit in size. However the first half of it doesn't matter because A17 is always tied to +5V. A17 is only present in 2mbit ROMs. That same pin is unused in 1mbit ROMs and is Vcc in 512kbit ROMs.
4. Intel 28F0x0 chip's Pin 1 should be either +5V for normal (read-only) operation or +12V for read-write operation. And this is exactly what JP3 is setting up: JP3 1-2 ties Pin 1 +5V, JP3 2-3 ties Pin1 +12V. When JP3 is unpopulated, it leaves pin 1 unconnected (which is OK for 29-series EEPROMs). Both JP2 and JP3 do absolutely nothing when the original 27C512 BIOS chip is used. Be careful: JP3 2-3 position will most likely damage 5V-only parts by sending 12V into them! My JP3 is 1-2. AFAIK these BIOSes do not write anything to ROMs, so no need to enable read-write mode.
5. I flashed my 2mbit file into 28F020 - and it freaking worked! Now I can choose between AMI and AWARD with the position of JP2! I have no idea how this is any useful tbh, but it's a fun concept at least =)

Attached below are some pics and a ZIP file with a DualBIOS image (1mbit and 2mbit variants).

pics

Original BIOS chip and how it fits into DIP32 socket:

New BIOS chip:

AMI:

AWARD:

Very interesting discovery about how to use two BIOS images on one EEPROM w/M912. I think my version of the MB already has the DIP-32 socket.

With respect to the J.2 AWARD BIOS...

Back in February, I started testing with the original PC Chips m912 v1.7 BIOS from 12/02/1994. This BIOS works out of the box with:

8 GB CF card w/LFB, 32-bit
Intel DX4 WB
does not work with Am5x86, even in 3x (blank screen)

With Intel DX4-100-WB, and without loading any other DOS drivers, I record 3376 KB/s for a 64 Kbyte tranfers in DOS.

With the J.2 BIOS, also using the Intel DX4-100-WB, I record 2476 KB/s for the same CF card. I've got block mode enabled in the AWARD BIOS, but there aren't any other speed settings. I am guessing that the IDE transfer rate is being put in PIO-1 or PIO-2, or 32-bit transfers aren't being used. I have the VLB I/O card setup for the fastest speed via the jumpers. There aren't any BIOS settings for IDE speed or 32-bit mode.

I compared cachechk timings to ensure the original AMIBIOS and AWARD BIOS were onpar w.r.t. L1, L2, RAM speeds, and they are.

M912 J.2. with Am5x86-133 and Cx5x86-133 run fine. However, on the pre-POST boot screen, the Am5x86-133 shows up as Enhanced Am486DX4-S at 100MHz, while the Cyrix shows up as Cx5x86-S CPU at 132 MHz. However, CHKCPU reports 133 MHz and Write-Back enabled. 8 GB CF card detects and boots fine. No issue with fake cache or incorrect cache being displayed after POST. However, IDE speed is abnormally slow at 2415 KB/s.

Both CPUs are able to run DOS benchmarks.

I then tested the AMI 1995X BIOS. Am5x86-133 and Cx5x86-133 work fine and report correctly. 8 GB CF card detects and boots fine. No issue with fake cache or incorrect cache being displayed after POST. IDE speed OK at 3376 KB/s.

Curiously, with both AMI BIOSes (original and 1995X), the IDE read speed is abnormally low only when using a Cyrix 5x86. Coretest reports 1852 KB/s, whereas with the Am5x86-133, it reports 3376 KB/s. The AWARD J.2 BIOS shows even lower with the Cyrix 5x86-133 installed, at ~1400 KB/s.

What I found most troubling was the Cyrix 5x86 massive IDE slow down. While this can probably be circumvented by using a SCSI card, it is a serious limitation.

I think Jan wanted to find solutions to these issues before releasing his BIOS. There's the Am5x86 IDE slow down speed compared to the AMIBIOS; there's the additional Cyrix 5x86 IDE speed slow down (worse than AMD 5x86 at the same core frequency); there's the POST screen mis-identification of the Am5x86 CPU as Am486DX4-100.

This is very good news.
Thanks guys!

Edit:
from my notes back in november 2021:

- 5x86 is better on 1995X
- 1995 X supports Am5-133
- 5x86 120 (@40mhz) is better than Am5 133 and 160 (40mhz)

I didn't test the HD speed. Thought it'll go as fast as the CF allowed...
I took notes in a way I do not clearly understand what I did (so much for doing things while doing others).

feipoa, the dual bios idea is the same idea I still have for the acard, haven't gotten around to it, yet.

also can't decide a good place to put the jumper.

weedeewee: I think the dual bios option would be even better on the ACARD 7722: for CD-ROMs, use the original BIOS and for HDDs, use v1.73. What we really need are the proper terminator blocks. Did you see the eevblog post with schematic for the correct terminators?

feipoa wrote on 2022-05-04, 20:24:

weedeewee: I think the dual bios option would be even better on the ACARD 7722: for CD-ROMs, use the original BIOS and for HDDs, use v1.73. What we really need are the proper terminator blocks. Did you see the eevblog post with schematic for the correct terminators?

Yes, I know that would be a great option for the acard. That's why I mentioned it on the m68k forum 😉

No I haven't seen the terminator thread on the eevlog site.
My guess at the moment is, it boils down to terminating, either actively (IC) or passively (resistors) the high bits (8-16) to be able to use the adapter on a narrow scsi bus without detection problems.
since I haven't gotten round to that either 😒

edit : read the eevblog, I was sort of right. Tying all the high bits together with one resistor to termpwr seems a bit odd, but heck, if it works, great.
Now gonna check the adapters I bought 😁
edit2: I'm gonna have to make an eevblog account aren't I... 😐