I'm not 100% confident in my solution but i will post what i found. I coud very possibly be wrong.
The original chips (currently on the card) are Fujitsu 81C4256A-60 256k x 4bit = 128Kb
The ram stick i found are made of HY514404A 1024k x 4bit = 512Kb
Here is a side by side picture of both datasheet. On the pinout section :
The attachment datasheet.png is no longer available
Besides the fact that 81C4256A labels its 4bit data pins DQ1 -> DQ4 (HY514404A uses DQ0 -> DQ3). The only difference is an extra address pin.
Pin 5 is not used on 81C4256A (nc -> not connected) while it's used as an extra address line (A9) on HY514404A.
When reading/writing data, row address is loaded first, then column address.
On 81C4256A, we have 9 bit row address and 9 bit column address
- 2^(9 + 9)
- 262144 == 256*1024 == 256k
- So 256k words of 4bit length (256x4) = 128Kb
On HY514404A we have 10 bit row address and 10 bit column address
- 2^(10 + 10)
- 1048576 == 1024*1024 == 1024k
- So 1024k words of 4bit length (1024x4) = 512Kb
So, my theory is that if i fix the A9 address line to zero, the chip will load row and columns on 9 address lines instead of 10. Making the chips virtually the same. (75% of HY514404A capacity is wasted, but i don't mind)
That's a long shot.... But electric signals are compatible. I will probably not burn my card. I must admit that i did not checked the timings... i'm assuming that 60ns EDO should be compatible with another 60ns EDO if the card uses "non aggressive" timings.
Again, i can be 100% wrong. I never swapped DRAM like that.
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