While i don't have detailed information about that can use EDO RAM:
Chicony TK8880F (BCT) Note: sees 64Mb EDO memory modules as 16Mb. Hmm ...
Biostar MB-8433UUD-A revision 2 (EYS)
Biostar MB-8433UUD-A revision 3.1 (EYA)
Shuttle HOT-433 version 4 (EYA)
PC-Chips M919 V3.4B/F (EYT)

2 that cannot:
Gigabyte GA486AM/S revision 2.20 (BTA)
Octek Hippo 12 VIP revision 1.01 (BCA)

So you are probably right.

* None of the other motherboards with earlier UMC chipsets (that i tried myself so far) can use EDO RAM.

It might be possible to look at the BIOS and figure out how it's determining whether to show or hide those options.

jakethompson1 wrote on 2022-05-31, 03:10:

It might be possible to look at the BIOS and figure out how it's determining whether to show or hide those options.

I already did so: It looks at the chip revision number stored in the PCI header and patches itself like MODBIN would do to enable or disable these options. I don't have any mapping between revision labels printed on the chip and electronic revision code labels, but I'm going to look up the threshold for "EDO" tonight in the BIOS code.

Might be interesting to check different BIOS versions too. I have a HOT-433 and my UMC8881 date/revision is 9548ETS. I tried three different BIOSs on it. IIRC, the board was always able to run with EDO installed, but only one BIOS had an option for enhanced timing for the EDO RAM, and enabling it caused memory performance to vastly improve.

bakemono wrote on 2022-05-31, 13:55:

Might be interesting to check different BIOS versions too. I have a HOT-433 and my UMC8881 date/revision is 9548ETS. I tried three different BIOSs on it. IIRC, the board was always able to run with EDO installed, but only one BIOS had an option for enhanced timing for the EDO RAM, and enabling it caused memory performance to vastly improve.

That's interesting. To be EDO compatible, the DRAM controller has to issue a dummy cycle (looks like the start of a write cycle) when it is done reading a burst from a page. This cycle is unneeded on FPM RAM, so you typically want to omit it to slightly improve memory performance. If a board works with EDO installed, it is a sign for the dummy cycle being issued, which is not the optimal configuration for FPM. At the same time, the slower read timing is not the optimal configuration for EDO. Sounds like the new north bridge defaults to a pattern that's compatible to both, but suboptimal on both types of RAM.

Furthermore, the initial RAM configuration is performed by the boot block, which might be at a completely different revision than the main BIOS. The coupling of boot block and main BIOS is very loose, so updating to a new boot block designed for some chipset is a quite easy and low-risk task, whereas updating the chipset support code in the main BIOS might be tedious, if the old chipset support code was already customized by the board vendor. So possibly all your boards used EDO-compatible boot blocks, while only one has an EDO-aware main BIOS.

Thank you. This certainly helps explain why nearly all 486 motherboards show no improvement with EDO memory installed.

feipoa wrote on 2022-06-02, 03:11:

Thank you. This certainly helps explain why nearly all 486 motherboards show no improvement with EDO memory installed.

I wonder if EDO support on late 486 chipsets was not so much about a performance improvement as needing to be compatible as the price of 16MB EDO SIMMs (in mass production at the time to build 32MB Pentium systems) may have dropped below FPM ones.
So it would make sense that some chipsets merely "tolerate" EDO RAM rather than taking advantage of the modified access timings.
Thoughts?

mkarcher wrote on 2022-05-31, 13:00:

I already did so: It looks at the chip revision number stored in the PCI header and patches itself like MODBIN would do to enable or disable these options. I don't have any mapping between revision labels printed on the chip and electronic revision code labels, but I'm going to look up the threshold for "EDO" tonight in the BIOS code.

EDO option is only available if the UM8881F reports revision code 4.

I guess we just need a means to translate the chip's surface markings to the revision code. Is there a simple DOS tool that the majority of users of the forum can run to determine the revision?

feipoa wrote on 2022-06-04, 23:14:

I guess we just need a means to translate the chip's surface markings to the revision code. Is there a simple DOS tool that the majority of users of the forum can run to determine the revision?

Anything that can list PCI devices including revision numbers, analogous to lspci -vmm on Linux, could do it. Perhaps SIV or HWINFO though I haven't tried. If all else fails, it would be a straightforward DOS program.

It looks like pretty much every hardware checking utility for DOS will list the chipset revisions. I'm attaching a freeware program which, after testing about a dozen, will list the revision with a single command and is quick to run without any sub-menu to navigate. Run the lspci.exe command from within the attached archives's DOS folder. You'll see something like:

100:10.0 Host bridge: United Microelectronics (UMC) UM8881F (rev 04)

To correlate the markings on the UM8881F chip, we will probably need to tabulate results. The particular rev 04 chipset I tested had these markings:

UM8881F
9639-EYA
M82832

When I get more time, I'll setup a testbed to tabulate more data from all my boards based on the UM8881 chipset. In the meantime, I've attached a simple DOS utility if anyone else wants to help.

Do we know which chipset revision supports Cyrix linear bust mode?

I ran some tests with various motherboards. The results are as follows.

Biostar MB-8433UUD v3
UM8881F
9639-EYA
M82832
Rev 04

Biostar MB-8433UUD v2
UM8881F
9623-EYT
R51537
Rev 04

Biostar MB-8433UUD
UM8881F
9540-ETA
133760
Rev 04

Biostar MB-8433UUD v2
UM8881F
9535-ETO
134730
Rev 04

Gigabyte GA486AM/S v2.21
UM8881F
9523-BCS
N42845
Rev 01

PC Chips M919 v3.4
UM8881F
9651-EYA
MB1948
Rev 04

PC Chips M919 v3.4
UM8881F (replacement)
9527-BTS
130760
Rev 01

Shuttle HOT-433 v4
UM8881F
9651-EYA
MB1327
Rev 04

Shuttle HOT-433 v1
UM8881F
9521-BTS
124040
Rev 01

Shuttle HOT-433 v1
UM8881F
9511-BCA
R11748
Rev 01

Looks like I have one other motherboard with the BTS revision (Rev 01). It is on a HOT-433 v1. I noticed that if I am using the latest AMI WINBIOS, the board functions correctly with EDO memory, even though it is not of Rev 04. However, if I use the HOT-433's AWARD BIOS, EDO memory does not function properly. Curiously, the M919 with the same BTS chipset does not function correctly with EDO and its WINBIOS. What does the BIOS on the Shuttle HOT-433 do to enable compatibility with EDO memory even though the chipset revision (Rev 01) does not support EDO?

What else I noticed from the data is that the datecode jump from Rev 01 to Rev 04 is a relatively short period of time (8 weeks), that is, 9527-BTS to 9535-ETO. I don't have enough data points, but I it is possible that there aren't any Rev 02 or Rev 03's. Maybe others here can fill in the gaps.

feipoa wrote on 2022-06-05, 08:21:

Do we know which chipset revision supports Cyrix linear bust mode?

On Award BIOSes, both the EDO stuff and the Cyrix linear burst mode stuff seem to be gated by "rev == 04" (Yeah, they compare for equal, not "greater or equal").

I guess that UMC might have intended to map rev 00 = A, rev 01 = B, rev 02 = C, rev 03 = D, rev 04 = E, and then decided to name the EDO-optimized revision "E" even though the next available letter would have been "C", and that's why we only see rev 01 and rev 04.

mkarcher wrote on 2022-06-06, 15:50:

feipoa wrote on 2022-06-05, 08:21:

Do we know which chipset revision supports Cyrix linear bust mode?

On Award BIOSes, both the EDO stuff and the Cyrix linear burst mode stuff seem to be gated by "rev == 04" (Yeah, they compare for equal, not "greater or equal").

I guess that UMC might have intended to map rev 00 = A, rev 01 = B, rev 02 = C, rev 03 = D, rev 04 = E, and then decided to name the EDO-optimized revision "E" even though the next available letter would have been "C", and that's why we only see rev 01 and rev 04.

Nice. I haven't dug into these compressed BIOSes much. So do these per-chipset-revision settings have a pointer in the settings table to a callback function that determines whether to show them? Or as you were alluding earlier, does something custom coded in the boot block patch the BIOS on the fly during the decompression/shadowing process?

It sure seems like the BIOSes are the closest thing to a datasheet that's ever going to come for these UMC chipsets.

jakethompson1 wrote on 2022-06-08, 02:26:

Nice. I haven't dug into these compressed BIOSes much. So do these per-chipset-revision settings have a pointer in the settings table to a callback function that determines whether to show them? Or as you were alluding earlier, does something custom coded in the boot block patch the BIOS on the fly during the decompression/shadowing process?

Shadow write protection can be temporarily or permanently disabled at any team, not only during the initial shadowing process. The boot block usually doen't even know enough about the runtime BIOS to be able to patch it. Remember that the core idea of boot blocks is that you can update the runtime BIOS while keeping the boot block, so a fallback mechanism in the boot block can help you recover from a bad flash.

Instead, the runtime BIOS during POST sometimes disables write protection for a short time to change shadow contents. I currently can't find wich BIOS hot-patched the EDO option, but I'm confident I've seen one. I have some BIOSes that have the EDO option permanently shown and some BIOSes that have the opton permanently hidden. Usage of the value from that option is gated by the northbridge revision. I do find BIOSes that detect the type of the onboard UMC Super-IO chip and adjust the available options in the CMOS setup, for example the GA-486AM BIOS dated 11/07/95.

feipoa wrote on 2022-05-24, 09:53:

Last week, I replaced the the UM8881F 9651-EYA chip on my PC Chips M919 with a UM8881F 9527-BTS chip.

Can you tell me if such a chip replacement can be done without any additional modifications, are both revisions pin-compatible? I want to proceed to replace revision 01 with revision 04 on the shuttle hOT-433 motherboard. My additional question is can I also replace the southbridge from AF to BF without modifications? Or more logically, do I need to replace the southbridge in the process or can I stay with AF?
Thank you for every answer.

I didn't have to do any modification of the board to use the BTS 8881F based chip in place of the EYA chip, but you are left with the limitations noted above.

I have not swapped southbridge chips between AF and BF. I suspect the BF has the PS/2 mouse support built-in, while the AF does not. Since the HOT-433 series expects the PS/2 mouse support to be on the keyboard controller chip rather than the southbridge, I'd suspect such a swap is OK. However, on a board like the MB-8433UUD, which uses the chipset for PS/2 mouse support, I hypothesis that using the AF would remove your mouse support.

Thank you,
so after all, here is my experience:

GIVER: Sowah Research SR-M401-A; UM8881F ETO/ UM8886BF DYS
RECIPIENT: Shuttle HOT-433 v1; UM8881F BCS (working with EDO but without option in BIOS)/ UM8886AF BYS

RESULT:
-(advantage) EDO is now available in BIOS options, however this option do not change anything in memory performance, even 0.1MB/s.
-(fault) on-board IDE controller causing hangouts on POST when HDD is connected to them.
-(fault) on-board IDE controller is recognized (Windows) as "absent/ missing" or "do not work properly".
-(neutral) with UM8886AF, on-board IDE BIOS setting max PIO3, with UM8886BF max PIO4.

CONCLUSION:
If you have UM8881F rev. 01 BCS (working with EDO) it is not worth your free time to make that mess 😉.

PS
Is UM8881F the fastest 486 chipset in FPU (games) aplications? PCI performance is quite good (~43MB/s with MATROX Mil 2) but memory.... SiS496/7 is ~10% faster in my tests (memory). Maybe some ACER chips have good both memory and PCI performance?

To confirm, the transplantation of UM8886BF onto HOT-433 v1 resulted in your onboard IDE controller not working, even when you force it to PIO-3 mode?

When you say the EDO option is not available in the BIOS, what wording is used?

Are you going to put the UM8886AF back onto the motherboard?

From my experience, the Acer boards have poor L2 performance.