Good catch, try moving the jumper 😀

Well that would be a different take on the "fake cache"
If you can find your chipset's datasheet you could probably read its registers and see what cache size the BIOS really programmed it for. Like was the BIOS deliberately set up to lie and say 256K.
When I was messing with one of my SiS 471 boards I read the datasheet in detail and what those cache size jumpers do is allocate address bits between the tag, bank select, and address lines of the cache chips, thereby increasing or decreasing the cacheable area.

Can you take a picture of your board ? Google shows no actual pictures of that board that I could find, would like to take a close look. Thanks.

Now that's interesting.
This might be from when people started to realize about take cache chips, so they decided to put on smaller (cheaper) cache chips instead of the full blown stuff.

So with the standard 8MB ram you wouldn't notice the difference any way, as it is all covered by cache. The jumpers were soldered to avoid people messing around and discovering the small cache. And the bios was modified to display 256kB ofc to avoid questions. The cave is soldered to avoid putting it on another board and discovering the same.

Another dirty way to save money for bad dealers. But saves less than actual fake chips.

jakethompson1 wrote on 2022-07-22, 20:35:

Well that would be a different take on the "fake cache"

Yep, this should be the case.
I've desoldered the wire jumpers and installed the jumper headers. It works as before when set to 64K, but fails to boot when I set it to 256K.

Found the alternative on the Mouser, will see if I can get some Renesas SRAM ICs.

Horun wrote on 2022-07-23, 01:57:

Can you take a picture of your board ?

Great pics! Good for ultimate retro database!

Unfortunately the cache chips are soldered. If quality control found problems due to single faulty chips they had two options: 1. throw these boards away, or 2. disable the faulty chips via soldered jumpers and sell the boards a little cheaper.
There are chipsets / BIOSes that report cache size by reding the jumpers btw.
I would desolder all 9 cache / TAG chips, insert DIL sockets and check for any defective chips - that could then be replaced easily.

There´s a reason why all decent mainboard manufacturers used sockets for cache and TAG.

majestyk wrote on 2022-07-23, 16:52:

There are chipsets / BIOSes that report cache size by reding the jumpers btw.

While it is possible that partially failed chips could be used in smaller config, the bios had to indicate 64KB size in that summary table shown when the DOS boot begins.
The problem is that BIOS shows 256KB cache while jumpers are set to 64KB, and this strongly smells like a fraud.

You mean they sold the boards as 256K, put some faulty chips in and made / forged BIOS to always report 256K? We cannot rule this out.
It would be very intersting to know how many of the chips are o.k.

majestyk wrote on 2022-07-23, 17:23:

You mean they sold the boards as 256K, put some faulty chips in and made / forged BIOS to always report 256K? We cannot rule this out.

Actually, we can be quite sure that the BIOS is misreporting the cache size intentionally. On early 486 boards, the cache size was a jumper-only thing, and only dual-bank configurations were supported, as bank interleaved mode was the only mode supported by the chipset. The chipset didn't even know how big the L2 cache is. These board typically used around five to seven jumpers for cache size configuration. A usual BIOS for this kind of board doesn't print the cache size at all.

On later boards, the external routing of address lines to the cache tag comparator (a part of the cache controller) got integrated into the cache controller. This means the routing, which needs to be different for different cache sizes, no longer can be influenced by jumpers, but instead needs to be configured by the BIOS. The amount of cache size jumper went down to three to four. These chipsets have a configuration register for setting the cache size and typically also support single-bank cache (a measure for cost reduction), becasue 4 chips take less PCB space than 8 chips, and 128KB cache is cheaper than 256KB cache. On a board with a chipset that needs cache size configuration, the BIOS detects the cache size, then it programs the chipset to use the cache size it detected, and finally prints the detected cache size to the user. If the system runs stable and all memory benchmarks confirm 64KB cache size, we can be sure the BIOS properly configured the chipset to 64KB cache size, so the BIOS knows that the board is set up for 64KB cache operation.

In any case, if the BIOS prints a cache size, and that cache size is different from the actual configuration of the board, I fail to see any plausible explanation except fraud.

Does anybody have solid info on Forex? I have a Spring Circle So5 VLB board with "Forex" chipset, but I always suspected it was a re-labeled OPTi chipset. Seeing they (or whoever used their name) are also into the fake cache business, I'm all the more suspicious that whatever my board may have, it isn't an original Forex design. Or were they really a thing?