Do you have a picture where all cache sockets are visible?

majestyk wrote on 2022-08-05, 12:45:

Do you have a picture where all cache sockets are visible?

Unfortionaly not 🙁
But i have a picture of the shematic. Maybe it helps ?
Otherwise i can disassmbly the computer in the evening so i can make better pictures.

The board photo on UR shows U32, U33, and U42 (though I notice you don't have a socket there. Maybe that's for dirty bit?) populated with 20ns Logic L7C164 16k x 4 SRAMs. Similar parts are QS8888, P4C188, MT5C6404, CY7C164.

At the moment you have 128K cache in Bank 1. The 4 chips need to be put into Bank 0 if the documentation is correct:

Second you probably will have to adjust the jumpering (red box)

Third the TAG chips U32 and U33 must be populated as "pancakepuppy" suggested.

Probably the board had 256K L2 cache plus TAG and someone pulled the 6 chips.

Ok thank you all very much for your help.

At this time it seems hard to find suitable chips here in germany.
Today i ordered 1 CY7C164-20PC
So i need to be patient until another chip are offered.

At the same time i ordered two chips with an higher refresh rate

IC CY7C164-35PC (so it shoud be 35ns)

Is it possible to use chips from different vendors if they are both 20ms or must both come from the same vendor or use the slower chips ?

The "higher refresh rate" actually means a slower memory chip. The nS value corresponds to frequency (f=1/t).
TAG RAM is generally allowed to be a step slower than L2 cache and some pictures show 25nS L2 chips so you could give the 35nS TAG-chips a try. It depends on the quality / selection of the chips you get. They might run stable or they might cause stability problems. With 20nS you´re on the safe side.

If your frontside-bus is 33 MHz this means 30.3 nS for the L2 cache chips -> 25nS chips are used
If your frontside-bus is 40 MHz this means 25 nS for the L2 cache chips -> 20 nS chips are used

As you can see slightly faster chips are being used to make sure tolerances don´t matter.

For TAG RAM I wouldn´t use 35nS chips at 40 MHz FSB, they might work at 33 MHz though.

Actually other way around. The tag cache is specified to be 5ns faster than the main cache chips, I saw that in number of motherboard manuals. But at the point if cache is 15ns, the tag ram is still 15ns.

Cheers,

pentiumspeed wrote on 2022-08-06, 00:18:

Actually other way around. The tag cache is specified to be 5ns faster than the main cache chips, I saw that in number of motherboard manuals. But at the point if cache is 15ns, the tag ram is still 15ns.

Cheers,

A typical COAST stick for eyample has both L2 and TAG chips soldered in the factory.

It´s for a maximum FSB of 66MHz so 6nS or 7nS L2 chips are present while the TAG chip has 15nS (sometimes 12nS).
This is also the case on countless mainboards.

Depending on the chipset there are several cache policies and methods to handle data in cache and TAG so maybe there are cases where both chips need to be made for the same frequency.
The L2 cache size necessary to cache a certain amount of RAM also differs between chipsets.

When I flip through my gallery I find several 486 mainboards with cache and TAG having the same speed like 20 or 15nS. I don´t know if these got fit in in the factory or if this was done to simplify production / sourcing.
But in many cases it looks like this:

The TAG chip has a slower speed than the L2 SRAM chips.
And I doubt that at this time (when 15 or 20nS chips were used for 486 boards) faster TAG chips with 7nS or 6nS were even available / possible to produce.

TAG speed dictates resulting latency, the slower it is the slower it takes for the chipset to look up if data is in cache
cache data chips speed translates to cache transfer speed

rasz_pl wrote on 2022-08-06, 15:58:

TAG speed dictates resulting latency, the slower it is the slower it takes for the chipset to look up if data is in cache
cache data chips speed translates to cache transfer speed

But obviously this doesn´t matter. If TAG latency was a bottleneck, manufacturers would have used TAG chips with the same or higher speed as the L2 chips.
They did not as I showed above.

some did, some didnt
counter example https://www.ultimateretro.net/en/motherboards/1111

That 12nS TAG schip was probably fit in by the same guy who screwed the screw of the heatsink - or 12nS 8Kx8 chips were cheaper / better available.
Later revisions of this BIOSTAR board with burst-SRAM had 15nS TAG chips (the Samsung "-13" chips are 7nS):

Glad you picked a 430FX board.
The INTEL application notes have all the info about the timings:

At no frequency are the TAG timings faster than the cache timings. They are slower and @ 66MHz equal.

(Same goes for the Burst SRAM case: All TAG timings are significantly slower.)

Here´s the full datasheet:
http://13.124.15.139/pdf/download.php?id=fd4b … =P&term=82437FX
___________________________________

Just for the record here´s another example, where TAG-RAM seems to be faster than cache-SRAM:

While the cache SRAMS do have 15nS read and write cycles, the TAG-chip - despite having "-12" in the name does in fact have 120nS read and write cycles!