maxtherabbit wrote on 2022-08-06, 14:55:

rasz_pl wrote on 2022-08-06, 14:50:

both memw and ior should be active at the same time, otherwise no transfer is taking place

that's not how it works, only one strobe can be active at a time

thats exactly how I/O DMA works on ISA bus http://wearcam.org/ece385/lecture6/isa.htm

leejsmith wrote on 2022-08-06, 15:37:

I had to drop the LA down to 1ms to see the memr data on the 286, but it was ok at 16ms on the pentium.
i will test them both again at 1ms

1ms? you mean record length? what frequency are you capturing at?
those long captures are useless because you cant see individual pulses
regardless, no memw means nothing is being stored to ram

leejsmith wrote on 2022-08-06, 15:37:

It just doe not have much activity on the memw

much? I dont see ANY activity during DMA on those captures

leejsmith wrote on 2022-08-06, 15:37:

until the end and it was the same when I looked with my scope.

you mean there are zero memw activity on the scope? even when you are running normal programs that write to ram? trace memw from ISA pin back to chipset, is there some buffer between that doesnt work or broken trace, is it shorted? measure resistance to ground/5V
that dosnt make any sense, no memw signal would also mean no graphic output 😮
how about /SMEMW? is this one also missing?

leejsmith wrote on 2022-08-06, 15:37:

should I be seeing a signal on memr when it has one on iow like the pentium.

look at http://wearcam.org/ece385/lecture6/isa.htm#4.0 for DMA read/write timing diagrams

even if memw was somehow missing soundblaster should be able to play sound as its using DMA in the other direction
>I tried my aztec sound galaxy and FM works, but no digital sounds
try LA capture while playing digital sound in DMA mode to see if there is memr/iow activity at the same time

>io ch ck
no idea about that, sorry

rasz_pl wrote on 2022-08-06, 17:24:

thats exactly how I/O DMA works on ISA bus http://wearcam.org/ece385/lecture6/isa.htm […]
Show full quote

maxtherabbit wrote on 2022-08-06, 14:55:

rasz_pl wrote on 2022-08-06, 14:50:

both memw and ior should be active at the same time, otherwise no transfer is taking place

that's not how it works, only one strobe can be active at a time

thats exactly how I/O DMA works on ISA bus http://wearcam.org/ece385/lecture6/isa.htm

leejsmith wrote on 2022-08-06, 15:37:

I had to drop the LA down to 1ms to see the memr data on the 286, but it was ok at 16ms on the pentium.
i will test them both again at 1ms

1ms? you mean record length? what frequency are you capturing at?
those long captures are useless because you cant see individual pulses
regardless, no memw means nothing is being stored to ram

I am talking about the frequency of the capture and I dropped it to the lowest it would go with this number of channels

leejsmith wrote on 2022-08-06, 15:37:

It just doe not have much activity on the memw

much? I dont see ANY activity during DMA on those captures

leejsmith wrote on 2022-08-06, 15:37:

until the end and it was the same when I looked with my scope.

you mean there are zero memw activity on the scope? even when you are running normal programs that write to ram? trace memw from ISA pin back to chipset, is there some buffer between that doesnt work or broken trace, is it shorted? measure resistance to ground/5V
that dosnt make any sense, no memw signal would also mean no graphic output 😮
how about /SMEMW? is this one also missing?

The scope matches the activity on the LA so I can see lots when the pc boots, when I do a HDD dir ect, but when I see no activity until the end of the floppy commands I also see nothing on the scope.

leejsmith wrote on 2022-08-06, 15:37:

should I be seeing a signal on memr when it has one on iow like the pentium.

look at http://wearcam.org/ece385/lecture6/isa.htm#4.0 for DMA read/write timing diagrams

even if memw was somehow missing soundblaster should be able to play sound as its using DMA in the other direction
>I tried my aztec sound galaxy and FM works, but no digital sounds
try LA capture while playing digital sound in DMA mode to see if there is memr/iow activity at the same time

>io ch ck
no idea about that, sorry

leejsmith wrote on 2022-08-06, 17:44:

I am talking about the frequency of the capture and I dropped it to the lowest it would go with this number of channels

no you arent, 1ms is 1khz 😀 capturing anything on ISA bus at 1 KHz is useless

leejsmith wrote on 2022-08-06, 17:44:

The scope matches the activity on the LA so I can see lots when the pc boots, when I do a HDD dir ect, but when I see no activity until the end of the floppy commands I also see nothing on the scope.

so there is memw activity when software is running on 286, but when you try reading floppy memw is flat? definitely trace it back to the chipset

One thing that is confusing me is it works with small files, I can load small files over and over from disk, I can read a disk dir it's only a problem with the file is over some size. If I can read small files everything is working.

did you perhaps get ISA memw pin wrong? 😀

leejsmith wrote on 2022-08-06, 18:45:

One thing that is confusing me is it works with small files, I can load small files over and over from disk, I can read a disk dir it's only a problem with the file is over some size. If I can read small files everything is working.

Maybe it has to do with a single-sector read vs. multi-sector read. With XT-IDE working presumably you can get into DEBUG?

Try:
debug
a
mov ax,0201
mov cx,1
xor dx,dx
mov bx,200
int 13
int3

g=100

When it comes back you should see number of sectors read in AX, and "NC" if carry not set and no error or "CY" if it's set, as given here: https://en.wikipedia.org/wiki/INT_13H#INT_13h … tors_From_Drive

If you hit an error then the upper 8 bits of AX should have an error code, which could be cross-referenced with the code in your BIOS to help dig further.

If one sector works, you can do a 100 and change it from 0201 to 0202 (for two sectors), 0203 (for three sectors), and so on.

This doesn't do any validation on the data returned (which will be at offset 200) so if everything comes back with no error then it's a different issue with data being corrupted only after the DMA transfer starts.

rasz_pl wrote on 2022-08-06, 17:24:

thats exactly how I/O DMA works on ISA bus http://wearcam.org/ece385/lecture6/isa.htm

You're right, I responded to that post without reading the context - didn't realise you were discussing 8237 DMA

rasz_pl wrote on 2022-08-06, 18:50:

did you perhaps get ISA memw pin wrong? 😀

I made up a PCB with headers on a dev card so it's the same pins as the pentium, also the timing on the LA is 1MS/s not 1ms

jakethompson1 wrote on 2022-08-06, 19:06:

Maybe it has to do with a single-sector read vs. multi-sector read. With XT-IDE working presumably you can get into DEBUG? […]
Show full quote

leejsmith wrote on 2022-08-06, 18:45:

One thing that is confusing me is it works with small files, I can load small files over and over from disk, I can read a disk dir it's only a problem with the file is over some size. If I can read small files everything is working.

Maybe it has to do with a single-sector read vs. multi-sector read. With XT-IDE working presumably you can get into DEBUG?

Try:
debug
a
mov ax,0201
mov cx,1
xor dx,dx
mov bx,200
int 13
int3

g=100

When it comes back you should see number of sectors read in AX, and "NC" if carry not set and no error or "CY" if it's set, as given here: https://en.wikipedia.org/wiki/INT_13H#INT_13h … tors_From_Drive

If you hit an error then the upper 8 bits of AX should have an error code, which could be cross-referenced with the code in your BIOS to help dig further.

If one sector works, you can do a 100 and change it from 0201 to 0202 (for two sectors), 0203 (for three sectors), and so on.

This doesn't do any validation on the data returned (which will be at offset 200) so if everything comes back with no error then it's a different issue with data being corrupted only after the DMA transfer starts.

As soon as i tried to read two sectors it locked up.

This is what I found today.
I can read anything smaller than 512k, but as soon as it goes over it will not work and locks up the system.
I have tried every ISA slot combination and it does not change.
Now just out of interest I removed the parity ram that is disabled via a jumper and it would not read anything from the A drive.

Now I have the cmos saving I can see the pc time is aprox 20 minutes slow since I set it at 1pm.

leejsmith wrote on 2022-08-07, 09:31:

the timing on the LA is 1MS/s not 1ms

that makes more and less sense 😀
Im sure you realize futility of sampling >8MHz ISA at 1MHz.

>I dropped it to the lowest it would go

because of memory depth, with higher sampling you couldnt see the end of transfer - do I get that right?
imo pentium.jpg 286.jpg are the only two captures that show something useful, and those are at 16MHz sampling.

regardless - there can not be a DMA transfer happening without memw present. I simply dont understand a situation in which:

-you can read small files and they return correct value
-simultaneously LA capture/scope shows missing memw

>I made up a PCB with headers on a dev card

try it in the first slot instead of last?

pdf you found in the video http://66.113.161.23/~mR_Slug/pub/datasheets/ … and/GC101-2.pdf shows integrated peripherals in GC101, and suggests no external buffering required, memr memw signals are directly slapped into the ISA slot.

The only suggestion I am left with is lifting first two ISA slots. They had green pins which you cleaned externally, but that green wicked from the bottom, there might be some nasty stuff between ISA plastic and pcb.

maybe he is sampling the 16-bit memory strobes and his system only asserts the ones on the 8-bit edge during floppy DMA?

maxtherabbit wrote on 2022-08-07, 13:43:

maybe he is sampling the 16-bit memory strobes and his system only asserts the ones on the 8-bit edge during floppy DMA?

nah, green blue probe wires are on B11 B12 ISA pins

rasz_pl wrote on 2022-08-07, 13:41:

that makes more and less sense :) Im sure you realize futility of sampling >8MHz ISA at 1MHz. […]
Show full quote

leejsmith wrote on 2022-08-07, 09:31:

the timing on the LA is 1MS/s not 1ms

that makes more and less sense 😀
Im sure you realize futility of sampling >8MHz ISA at 1MHz.

>I dropped it to the lowest it would go

because of memory depth, with higher sampling you couldnt see the end of transfer - do I get that right?
imo pentium.jpg 286.jpg are the only two captures that show something useful, and those are at 16MHz sampling.

regardless - there can not be a DMA transfer happening without memw present. I simply dont understand a situation in which:

-you can read small files and they return correct value
-simultaneously LA capture/scope shows missing memw

>I made up a PCB with headers on a dev card

try it in the first slot instead of last?

pdf you found in the video http://66.113.161.23/~mR_Slug/pub/datasheets/ … and/GC101-2.pdf shows integrated peripherals in GC101, and suggests no external buffering required, memr memw signals are directly slapped into the ISA slot.

The only suggestion I am left with is lifting first two ISA slots. They had green pins which you cleaned externally, but that green wicked from the bottom, there might be some nasty stuff between ISA plastic and pcb.

No matter what the LA speed is set to it does not show memw until the very end and I double checked this on my scope.
I just moved all cards around and no combination changed, but the first 8bit slot does have some probelms and the xt-ide would not work in it so I am going to remove it and check.

I can zoom into the LA files as close as you want if it helps

maxtherabbit wrote on 2022-08-07, 13:43:

maybe he is sampling the 16-bit memory strobes and his system only asserts the ones on the 8-bit edge during floppy DMA?

The memr and memw on the 16bit part of the isa match the ones on the 8bit section

I keep looking at the GC101 datasheet and it has

memw pin 29 - tristated when CPU hold, means inactive during DMA
This is precisely what we are seeing

smemw pin 27 - buffered memw
in theory same signal, but limited to first MB address space

Xmemw pin 99 - DMA dedicated one
and this is somehow missing!

page 47 is pathetically low res, cant see where it is going 🙁

btw board CRG found:
https://www.ultimateretro.net/en/motherboards/5241 Help identifying Headland Motherboard Model
another two very close boards:
https://www.ultimateretro.net/en/motherboards/9810 looks like there was a version with ami bios
https://www.ultimateretro.net/en/motherboards/10689
main difference is above GC101, yours has 3 discrete ttls, one has PAL, and the last one empty space 😮

GC101 pin 99 Xmemw goes right above GC101. Looking at your video @9:19 it then turns left in the direction of power connector and disappears in a via
Can you solder a probe wire to GC101 pin 99 (I mean wherever that via leads) and do and capture? or just check it it should go to ISA and is broken somewhere on the way

rasz_pl wrote on 2022-08-07, 14:33:

I keep looking at the GC101 datasheet and it has […]
Show full quote

I keep looking at the GC101 datasheet and it has

memw pin 29 - tristated when CPU hold, means inactive during DMA
This is precisely what we are seeing

smemw pin 27 - buffered memw
in theory same signal, but limited to first MB address space

Xmemw pin 99 - DMA dedicated one
and this is somehow missing!

page 47 is pathetically low res, cant see where it is going 🙁

btw board CRG found:
https://www.ultimateretro.net/en/motherboards/5241 Help identifying Headland Motherboard Model
another two very close boards:
https://www.ultimateretro.net/en/motherboards/9810 looks like there was a version with ami bios
https://www.ultimateretro.net/en/motherboards/10689
main difference is above GC101, yours has 3 discrete ttls, one has PAL, and the last one empty space 😮

GC101 pin 99 Xmemw goes right above GC101. Looking at your video @9:19 it then turns left in the direction of power connector and disappears in a via
Can you solder a probe wire to GC101 pin 99 (I mean wherever that via leads) and do and capture? or just check it it should go to ISA and is broken somewhere on the way

I traced /XMEMW and /XIOW over to the math co pro socket and I will find /SMEMW tomorrow.

leejsmith wrote on 2022-08-07, 17:25:

I traced /XMEMW and /XIOW over to the math co pro socket and I will find /SMEMW tomorrow.

WTF ... so that would mean everything is working as it should, and Headland chipset is simply unable to support DMA to RAM on expansion cards.
your defect must be something else then 🙁, like the corrosion under ISA slots, and not just the first two considering battery was on the bottom but somehow wicked all the way across.

rasz_pl wrote on 2022-08-07, 18:15:

leejsmith wrote on 2022-08-07, 17:25:

I traced /XMEMW and /XIOW over to the math co pro socket and I will find /SMEMW tomorrow.

WTF ... so that would mean everything is working as it should, and Headland chipset is simply unable to support DMA to RAM on expansion cards.
your defect must be something else then 🙁, like the corrosion under ISA slots, and not just the first two considering battery was on the bottom but somehow wicked all the way across.

I guess my next job is to remove the 8 bit isa slot.