Among my (small) collection of Intel 430HX mainboards is a ECS P5HX-A (Rev. 2.3), the larger ATX brother of the more common P5HX-B.

I´m currently using it for testing my 128MB SIMMS
Any chance repairing 128MB FPM-SIMMS with parity?

It has 256K L2 cache onboard, a COAST slot and a second 32-pin DIL socket for TAG-RAM. The classical HX setup.
While at it I thought why not uprade this L2 cache to 512K so I can enjoy the full cacheable area of 512MB RAM?
According to the manua it´s a piece of cake: Just insert a 256K COAST-stick (COAST version 2.0 or higher) or - as ECS prefers - the ECS "CM161".
I own a couple of CM161, but they are all 512K. So I tried a lot of sticks from my collection. They would either be not detected, the system wouldn´t start, or after recognizing 512K cache, they could not be used - test programs as cachechk, speedsys or ctcm7 would hang or report a cacheable area of 64MB.
With the original BIOS a 512K COAST stick is being detected properly but won´t work correctly.
With the later "n" and "q" BIOS, the system refuses to POST or report "none" or "256K" as L2 cache.
After testing about 30 sticks I gave up on this and tried to find a CM161 with 256K. These sticks seem to be very hard to find.

Since this mainboard was available with 256K or 512K onboard cache I decided to upgrade onboard cache instead.
First I removed the original chips (2x 32Kx8 7nS), then inserted two new chips (64Kx8 6.6nS). The 2nd TAG-RAM socket got populated with 32Kx8 15nS DIL-chip.

Of course the system wouldn´t boot after that 🙁 just like with most 256K COAST sticks before.
By trying all different vacant resistor positions I found R257 (near the MCH) needs to be 100R. Now the system started but detected the new L2 chips as 256K - just like before the upgrade. But now it played well with all different COAST sticks for a total of 512K. The missing resistor probably had been the problem all the time.

BIOS not detecting the full cache size turned out to be a far more difficult issue to solve.
I first compared the datasheets of the old chips ( Mitsubishi M5M5V1132FP) and the new chips (Micron MT58LC64K32B3) pin by pin. There is perfect compatibility except for the address-bus.
The 32Kx32 chips have 15 address lines (A[14:0]) while the 64Kx8 chips need 16 address lines (A[15:0]). The last address line is at pin 49 tha is "NC" at the 32Kx8 chips.
While inspecting that area I found a vacant resistor position at pin 49. For testing I insert6ed 10K, 1K, 100R and 10R but as soon as a any resistor was present BIOS reported "none" for L2 cache.
Because of this result I inspected the traces and other components for hours, but couldn´t find a solution.

Then I remembered that these address lines must be present at the TAG chips also. And they were, except for A15 that must be connected to the second TAG chip - but wasn´t.

The A15 line is very difficult to trace, it changes sides at several Vias, is hidden in some layer inbeween and surfaces where you would least suspect it. A second 0 Ohm resistor must be populated near the TAG RAM plus the resistor at pin 49 must be present. the latter one connects A19 to the HX-Northbrige the first one to the 2nd TAG chip.

Now all present cache gets detected correctly and is 100% functional, the cacheable area is finally at 512MB.

For some reason only known to the ECS developers the 3.3V "VssQ" I/O output buffer power supply pins are connected to the output of the Vcore VRM, not the VI/O VRM, so they are hooked to 2.8V at the moment. The VssQ voltage is rated for Vcc +/- 0.3V.
Vcc is rated for 3.13 - 3,6 so the minimum is 2.83V. If a Pentium MMX is running at 2.8 or 2.9V I would consider this a stable situation, but when you do some VRM mod here to run a K6-2 or K6-2/III+ L2 cache will become unusable.