VOGONS


First post, by Blavius

User metadata
Rank Newbie
Rank
Newbie

Man, I was hoping to write this topic when I had something working to show off, but no dice. Anyway, I thought it would be worthwhile to at least share what I did and get your thoughts on it, if only to understand what I missed.

I have a IBM PS/2 P70, a luggable with a plasma screen, which I think is a pretty neat machine. Its main downside is the stock 386 16MHz, which makes it pretty slow for things like doom and win95. As most of you know, there are lots of cool upgrades out there; souped up 386's with cache (e.g. 486DLC, 486DRX-2), plug-in modules with an actual 486, and even microchannel cards that take over part of the system entirely. The problem is that most of that stuff is just plain impossible to find - even if you would be willing to pay the prices asked when they do come around.

The only properly available option on ebay are the Cyrix 386 based solutions. Unfortunately, those are generally ticking at the board frequency. The clock-doubling ones that really give a boost to your system, I haven't seen on offer even once. So - I ended up with a TI486DLC. I'm not unhappy with it; its 8kb of L1 cache gives about a 50% performance boost. But still, it's frustrating to know there is much upward potential left. Also, I have some bad experience overclocking PS/2's, so I got stuck.

When I was browsing though 386 upgrade modules (those sporting a proper 486), I noticed one had a 'clock double' jumper. This made me think; what if I could double the clock frequency of my 486DLC externally? This would mean intercepting the board frequency on the way to the processor, doubling it, and feeding it back in. The assumption here is that the processor knows what to do with this; the other components in the system still tick at their original frequency.

The first step was to figure out a way to double the frequency. I found a nice article that used a comparator and XOR gate to achieve this, and adapted it to the frequency I needed. After a lot of experimenting, it turned out not to work too well, as the comparator used was not fast enough to output a proper square wave, but a sine instead. After a lot of tuning I managed to get the circuit to work kindof alright; it outputs a 66MHz sine out of a 33MHz clock, but the peaks are not perfectly symmetrical.

IMG_3795.JPG
Filename
IMG_3795.JPG
File size
53.22 KiB
Views
723 views
File license
CC-BY-4.0

The second step was to jam it into an interposer. I cut the pin carrying CLK2, connected it to the circuit, and feed it back into the top socket.

IMG_3790.JPG
Filename
IMG_3790.JPG
File size
86.21 KiB
Views
723 views
File license
CC-BY-4.0
IMG_3792.JPG
Filename
IMG_3792.JPG
File size
58.92 KiB
Views
723 views
File license
CC-BY-4.0

On this goes the TI486DLC, and the whole contraption goes into the motherboard:

IMG_3794.JPG
Filename
IMG_3794.JPG
File size
79.04 KiB
Views
723 views
File license
CC-BY-4.0

But this is where the fun ends. The computer doesn't post. The processor does get warm, so it at least gets power, but there is no output on the screen. When I removed the interposer and reinserted the CPU directly it again came up happily.

So, it just doesn't work. Question is why. I see two options:
1. It could work, but I didn't do it right. Maybe the 66MHz I generate doesn't have the right flanks/uptime etc.
2.There is some fundamental reason it doesn't work. Perhaps clock doubling requires some sort of buffering to interact with the rest of the system, e.g. sending the 'ready' signal only every other pulse.
Curious to hear your thoughts!

Reply 1 of 12, by H3nrik V!

User metadata
Rank Oldbie
Rank
Oldbie

I can think of 2 plausible reasons

1. The square wave, which is not square. This could however as well be an issue with your scope, though.
2. Doubling the clock on the clock in will also result in address/data activity derived from the higher clock, thus not being in sync with anything else on the motherboard.

Please use the "quote" option if asking questions to what I write - it will really up the chances of me noticing 😀

Reply 2 of 12, by Anonymous Coward

User metadata
Rank l33t
Rank
l33t

Cyrix had a product called 486DRu. It came out just before the DRx2, and was a kit consisting of a normal 486DLC and an interposer with built in clock doubler and cache coherency. I would see if you could find somebody willing to provide you with high resolution pictures of one of those. Maybe it could be reverse engineered. CPU-World would be a good place to start.

"Will the highways on the internets become more few?" -Gee Dubya
V'Ger XT|Upgraded AT|Ultimate 386|Super VL/EISA 486|SMP VL/EISA Pentium

Reply 3 of 12, by Blavius

User metadata
Rank Newbie
Rank
Newbie

Unfortunately I didn't take a picture of the original waveform, but it was not a square wave but a rounded off triangle, almost a sine. For this reason I added a second comparator to try to make the circuit work with the RC time delay. Unfortunately this did nothing as the output of the comparator is also almost a sine at this frequency. The XOR gate is fast enough though, and with the time delay caused by the gate and some tweaking of the comparator threshold voltages I got the result shared above. As the 66MHz flank coincides with the clock flank I figured it would be good enough.

The syncing might be the real culprit. Never heard of the 486DRu, but it sounds very interesting. I tried my best on Google but could not find any picture of it. It seems to be quite elusive. I'll check on CPU-world if someone even has one, and then hope the pictures give some clues. Perhaps to be continued 😀

Reply 4 of 12, by Sphere478

User metadata
Rank l33t++
Rank
l33t++

Can you use a capacitor or something to induce a delay. If you can make it fall behind to the previous peak it may be the same as syncing.

Btw:
Re: Socket 5/7/SS7 (clock signal interposer) Tweaker (Research)

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 5 of 12, by pshipkov

User metadata
Rank Oldbie
Rank
Oldbie

The 40MHz rated Cyrix DLC processors barely hit 50MHz overclocks, let alone 66.
Lower the base frequency to 20MHz (40MHz to CPU) before looking at other signal/logic issues with the mod.

retro bits and bytes

Reply 6 of 12, by Blavius

User metadata
Rank Newbie
Rank
Newbie
pshipkov wrote on 2022-09-04, 18:37:

The 40MHz rated Cyrix DLC processors barely hit 50MHz overclocks, let alone 66.
Lower the base frequency to 20MHz (40MHz to CPU) before looking at other signal/logic issues with the mod.

Ah, I should have clarified; the crystal in the system ticks at 33MHz, and the processor halves this to 16MHz. So, to have the processor run at double the speed (33MHz), I need to double the frequency that goes into it to 66MHz. Sorry for the confusion.

Reply 7 of 12, by Blavius

User metadata
Rank Newbie
Rank
Newbie
Sphere478 wrote on 2022-09-04, 18:21:

Can you use a capacitor or something to induce a delay. If you can make it fall behind to the previous peak it may be the same as syncing.

Btw:
Re: Socket 5/7/SS7 (clock signal interposer) Tweaker (Research)

In my case the capacitor mainly attenuates the signal thanks to the sine wave. In the article I shared they have a block wave input, use a capacitor to delay it into a triangle and then use a comparator to turn in back into a block. Problem is the comparators are not fast enough to do this reliably. At 500KHz the original doubler circuit runs fine.

Thanks for the link, I wasn't aware of that thread!

Reply 8 of 12, by Sphere478

User metadata
Rank l33t++
Rank
l33t++

What about using a clock generator? And using the bus clock as a crystal input? Just find one with a 2:1 ratio?

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 9 of 12, by Tiido

User metadata
Rank l33t
Rank
l33t

The system must use same clock as CPU receives, almost all signals that the chipset need are synchronous to CPU clock. So what was done will never work, the rest of the system needs the higher clock also.

T-04YBSC, a new YMF71x based sound card & Official VOGONS thread about it
Newly made 4MB 60ns 30pin SIMMs ~
mida sa loed ? nagunii aru ei saa 😜

Reply 10 of 12, by rasz_pl

User metadata
Rank l33t
Rank
l33t
Tiido wrote on 2022-09-04, 20:01:

The system must use same clock as CPU receives, almost all signals that the chipset need are synchronous to CPU clock. So what was done will never work, the rest of the system needs the higher clock also.

this, if anything find the source of CPU clock (you said 33mhz generator) and replace it by inject faster clock there

Open Source AT&T Globalyst/NCR/FIC 486-GAC-2 proprietary Cache Module reproduction

Reply 11 of 12, by kixs

User metadata
Rank l33t
Rank
l33t

Standard Ti486DLC has 1kb of L1 cache. Ti486SXL has 8kb and there is also double clock version of it Ti486SXL2. If someone is really looking for it, it shouldn't be too hard to find.

Requests are also possible... /msg kixs

Reply 12 of 12, by Blavius

User metadata
Rank Newbie
Rank
Newbie

In the thread that Sphere linked to galanopu mentions the following:

There is probably also a mid-road solution were you use a pll to exactly double the clock, this should be generated from the normal clock input.
In this case again you need to process correctly some signals (handshaking) but in general not all + no extra delays on the bus.

If the notion of the 486DRu being a interposer with an ordinary 486DLC on it is correct, it should roughly do what is mentioned above. In any case, clock doubling processors don't require any adaptions on the motherboard, so it is possible to double a clock - somehow. Based on what you all said, it's likely these processors have some extra logic to fix the syncing. The real question is what exactly that is.

Being able to electrically reverse engineer the DRu interposer would be the best case, doing it based on pictures could also work - IF only ic's with predefined functions are used. Without that it becomes a guessing game which handshake bits to modify, and crucially how. Maybe switch them off every second processor clock tick? Hard to say, and difficult to diagnose what you got wrong if it doesn't work.

I'll try to get pictures of the interposer. Without that, or some old-time guru stepping in that knows exactly how to do this, this seems impossible.