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Reply 220 of 1198, by Blavius

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Sphere478 wrote on 2022-09-10, 19:46:

If someone wants to post kicad footprints with nets of the two sockets, I might tinker with this a little. (If it is welcome)

No promises,

I’m thinking pin header stack. Two double layer pcbs probably.

You can find the netted circuit and footprints in the attached project. It would be great to have someone with more experience look at this.

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Reply 221 of 1198, by feipoa

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I'd suggest a single 4+ layer PCB to reduce trace size. When I did a comparison of an Evergreen interposer with QFP144 SXL2-66 chip, which has a single PCB of very tight integration, compared to a double-PCB Gainbery interposer stack, I had better luck at 80 MHz in more motherboards with the Evergreen. And in a few cases (2), the unit with the double-PCB interposer would not work even at 66 MHz. Another idea is to create two versions, one with double PCB's and one with a single PCB.

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Reply 222 of 1198, by Sphere478

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https://youtu.be/_Z6XSI53ZJg

^Wow yeah, that pinout is waaaaay different 🤣

As far as Looking at this for a single pcb:

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There isn’t much room to run traces, heck the ground planes won’t even connect. Let alone be able to route all those nets. Also, I’m not sure how you would solder it with one pcb.

Sparing some kinda brilliant idea, looks like we gotta do pin headers. Or use a side by side pcb like Blavius made. (Which I understand is working well?)

Last edited by Sphere478 on 2022-09-11, 08:39. Edited 1 time in total.

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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Reply 223 of 1198, by Sphere478

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This is just a super sloppy sketch of what I am thinking.

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I believe this should be possible and relatively easy to assemble. A little complicated to route the traces though, but looks doable.

Four layer might be nice so we can keep the signals spaced out and put ground planes all over.

Smd mounting of the sockets is possible and would possibly allow a single pcb design but that would be quite a trick to solder.

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 224 of 1198, by feipoa

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I suggest reading through this thread to get caught up on what we've already discussed. Otherwise, I will have to continually hunt down already present information and re-paste it again (as I've been doing).

In regard to the two PCB's, here's a comment from one of the previous designers of the single-PCB interposer.

cb88 wrote on 2019-08-14, 19:36:
maxtherabbit wrote:

IMO tiido still has the right idea with 2 PCBs

yeah it might increase the board cost a little but that's easily worth it relative to having to deal with reflowing heinous SMD PGA sockets and pin headers. it would also make routing much easier

thanks for posting the kicad schematics and symbols - I might take a crack at it now

Nah thats nonsense... nobody else has ever done, EVER that for a reason. It's just more work... you'd always just use a 4-6 layer board instead. Reflowing the BGA packages is trivial... you should be able to do it with a hot plate or hot air gun relatively easily.

Also I do intend to continue with my design... it just isn't one of my priorities it's a hobby after all.

As discussed, on page 7, if you align the PGA-132 up against the PGA-168, you will see that there's really only two sides which may be more challenging to solder, but hot air and solder paste should negate most of that difficulty. The idea was to use single row pins rather than whole sockets to make hand soldering possible, however someone with the appropriate heating contraption may be able to use whole sockets.

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As shown previously on pages 8 and 9, here are the commercial product photos of what we are wanting to replicate. Unfortunately, these are so rare that it has eluded me thus far.

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If a 4-6 layer single-PCB board is beyond your desire, that's no problem, I'd be more than happy to test out a double-PCB prototype. However, if it fails at 80-100 MHz, I'd be left wondering, maybe a single PCB design would have worked.

Plan your life wisely, you'll be dead before you know it.

Reply 225 of 1198, by Sphere478

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I kinda mentioned what you talked about, where a smd single pcb should be possible, I just feel that most people will have a lot of trouble assembling it I certainly would have trouble. But if you feel up to it, replicating the commercial product’s pcb (which appears to be smd) is of course possible.

Tryin to help man. Just brainstorming here. Saw the footprint upload and played with it a little in kicad in a free moment and typed some thoughts

On a single pcb through hole style, there isn’t much room between the pads for routing. With enough layers it may be possible though. Reducing the flood clearance does allow the flood through and routing a trace doesn’t generate a drc so. Perhaps one layer for x, one for y and two for xy (diagonal) for the signals. And two more for the power. So 6 layer.

I am playing with thru hole style stacked single pcb idea as I type this when I should be sleeping 🤣 it looks like 6 layer is possible. Gonna have to use quite a few vias to untangle it though.

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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 226 of 1198, by maxtherabbit

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I'd like to point out that the guy who claimed I was posting "nonsense" also claimed that BGA work was "trivial" and also failed to deliver anything in the end

Reply 227 of 1198, by Blavius

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Just a general question concerning the stack; where do you guys find SMD sockets and square pin arrays? All I find on eBay is tru-hole.

I tried a couple of things to get the cache working, but so far no dice. I do have to say, I never got it to work 100% stable with a 486DLC on this machine either.

To complicate things, only cachecheck runs on this machine - speedsys crashes during startup.
-I had a MCA memory expansion card with another 8MB RAM, removed that, no improvement
-I bridged the VRM, and the CPU is now running at 5V. It gets a lot hotter, but no change on the cache
-I tried BARB, doesnt seem to do anything in cachechk or doom score.
-FLUSH doesnt do anything. If I define an exception area (like I do on the 486DLC) the system becomes unstable
-Blocking the first 64kb of each 1MB doesnt change anything

feipoa wrote on 2022-09-10, 10:43:

I also wonder if you've read through the Evergreen Rev-to-486 manual in detail? Look specifically at the information for the TI upgrade, not the IBM unit. You will need to use the 486cache.exe and revto486.sys files. You have options to disable the cache during the processing of user specified hardware or software interrupts, for example. You can also tell it to use BARB with just a particular interrupt, or to flush the cache upon entering/exiting an interrupt.

I have not. Could you perhaps share the manual and the software?

Reply 228 of 1198, by feipoa

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Bravius:
I don't have any SMD PGA-168 sockets. My hope was to use through-hole sockets.

I tried to attach the manual, but there is a 5 MB attachment limit on this forum. If you could please PM me your e-mail address and confirm your attachment size limit, I'll forward the manual via e-mail.

Sphere478:
Thanks for your interest! From what I've seen with these home brewed projects that turn out well, the majority of users who want it won't buy it if they need to assemble it. They want it fully assembled. So the difference in the number of users who won't want the PCB based on a slightly more difficult solder job, I predict, is very minimal. If you have the time and motivation, I would be more than happy to test out both design configurations.

Regarding footprint, I think user cb88 uploaded files for a unit with space for the VRM, etc. There was discussion about using a mini DIP switch for different voltages, but perhaps a through-hole trimmer is best for a first go. There's been a lot of discussion on the numerous possibilities in this thread, but unfortunately, over the years, the details have escaped me.

Plan your life wisely, you'll be dead before you know it.

Reply 229 of 1198, by Sphere478

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Still no promises, but if I get time what method do you want me to focus on first? Smd pads? Thru hole style? I gather you don’t like the pin header option? Fourth option?

I’ve kinda got a urge to see if I can route the thru hole method. 8 layer may be able to eliminate intermediate vias btw, thoughts on this? I think 6 layer is possible. 4 layer probably not.

6 layer will take up the center with many vias it seems though. So a center mounted vrm probably won’t happen.

I’d like to have mostly unobstructed power planes but if you feel that we can sacrifice here, 4 layer may become slightly more possible. Though I still think it will not only be a mess but a long shot at all. So 6 or 8 layer is my vote atm.

Which side gets the parts for the vrm btw. Do you have a preference?

Also are there any lines or pins that need switches? Like for multiplier or etc? Any tweaks that you want to add?

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 230 of 1198, by feipoa

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My first preference is using through-holes for both the PGA-168 and PGA-132 mounts and a single PCB. I remember thinking long and hard about this years back and determined that I could even assemble it without hot air, but now that I am comfortable with solder paste and hot air, I'd likely use this to save time. I think the VRM, trimmer, header, and tantalum should be on the edge of the PCB like that shown for the commercial product above. This allows the VRM to cool some using an affixed fan. I never thought sandwiching the VRM under the CPU was a good idea. I'm not sure what the printed cost difference is between a 4, 6 and 8 layer PCB on a 10-unit order, so I cannot say which is preferred. I think using SMD sockets is not a great idea unless we have a single source [a person here] who can solder them on. Maybe some low melting temp solder paste would work, while not melting the plastic on the housing?

I do not have a preference for which edge of the PCB sticks out to receive the VRM/trimmer/header/tantalum. I think the tantalum might need to be moved to the centre if the VRM/trimmer/header consume too much real-estate. The header would be 3-pin, one for MEMW, the other two for 5 V and GND (fan). There are no multipliers which would use jumpers.

For assembly, I'd first try using rows of machine pins, as those shown above. Test the unit to ensure functionality at 80 MHz, then on a second PCB, see if I can use the proper PGA sockets w/hot air.

Someone mentioned about the possibility of needing to use same trace lengths for, I think, address and data lines. Is this needed? Max CPU operating frequency would be 100 MHz. Also mentioned, there may need to be more filtering caps underneath for each Vcc?

By the way, I should still have a dozen or so of the SXL2-66 PGA-168 chips held for me for this project.

Second overall choice is the double PCB method.

Thanks again.

Plan your life wisely, you'll be dead before you know it.

Reply 231 of 1198, by Sphere478

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Equal length would be ideal.

Let’s see if we can even get them connected first.

4 layer is pretty cheap, 6 layer is a little more pricy. 8 gets a little pricy from my recollection.

Yeah we can add caps in spare spots for gnd/vcc

Btw, we could probably add a fan header between 5v and gnd.

The more ground and isolation we can fit between the traces (and equal length) the better the signal should be.

I believe we are primarily dealing with fsb mhz here, does not the core mhz kinda hang out in the core?

In any case, 486 is a lot more forgiving than socket 7 and later. Stuff started to get wild in socket 370

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 232 of 1198, by Sphere478

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X, Y, XY, YX routing seems to work. (Barely)

Equal length might be a challenge.

Thoughts?

There are some DRC errors with the vias it seems, will have to look into that.

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Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 233 of 1198, by maxtherabbit

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if you can actually make it work with one PCB and two THT sockets, I don't think equal trace length will be terribly important

the distances will be so short overall as to not be relevant at these speeds

Reply 234 of 1198, by Sphere478

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maxtherabbit wrote on 2022-09-12, 00:43:

if you can actually make it work with one PCB and two THT sockets, I don't think equal trace length will be terribly important

the distances will be so short overall as to not be relevant at these speeds

I was kinda figuring as much.

First goal is to get them connected ….then go back and spend hours optimizing the routing 🤣

Finally, with 6 layers, x, y, xy, yx, gnd, vcc3. I gotta figure out where 5v is gonna go. (Unless you wanna power it externally, which I don’t imagine is ideal.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 235 of 1198, by feipoa

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Sphere478 wrote on 2022-09-11, 21:12:

Btw, we could probably add a fan header between 5v and gnd.

The "header" I mentioned previously is, in part, for a fan. 3-pin header: MEMW, 5V, GND.

feipoa wrote on 2022-09-11, 20:53:

I think the VRM, trimmer, header, and tantalum should be on the edge of the PCB like that shown for the commercial product above.

Sphere478 wrote on 2022-09-11, 21:12:

I believe we are primarily dealing with fsb mhz here, does not the core mhz kinda hang out in the core?

I recall we've discussed this to some extent in this thread. I don't fully understand the whole 286/386 FSB scheme. On all my 386 boards, if I am running a 100 MHz crystal oscillator, for example, the FSB is 50 MHz, or half the crystal osc. However, in the past, when I've measured the frequency going into the CPU, I recorded 100 MHz. So do 386 CPUs normally halve the incoming frequency? And clock doubling CPUs merely not halve it? If the later, then the freq. on the PCB would be 100 MHz. Or maybe the scope was seeing more than one frequency superimposed, e.g. 50 Mhz and 100 Mhz and I just saw the 100 Mhz freq, not looking for the 50 Mhz freq? I don't know. 286's are weird like this as well. On my 286, if there's a 100 MHz crystal oscillator installed, the FSB is 25 MHz, or quarters the crystal osc. For the interposer, best case, the FSB on the interposer would be 50 Mhz, worst case 100 Mhz. Maybe someone else could answer this better? Does planning for 80 or 100 Mhz complicate things with the layout requirements?

Plan your life wisely, you'll be dead before you know it.

Reply 236 of 1198, by Sphere478

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Idk if I have the answer to that, I kinda feel like it’s a moot point though, because we are pretty confined with what we can physically do by deciding to do dual thru hole on a single pcb in a stacked configuration. Perhaps someone can run a circuit simulator on what I come up with.

Not trying to talk you out of it, I think it has a decent chance of working actually, from what I am seeing anyway. Pin spacing and routing will be similar to socket 7 and 370 clearances and that works at higher frequencies but probably with more consistent routing lengths haha anyway, I still think that assembly will be our greatest challenge. Pre ss7 frequencies and sockets are more forgiving. Heck, this is a thing:file.php?id=134176&mode=view pretty sure there are pictures of someone running it on ribbon cables somewhere haha.

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 237 of 1198, by Sphere478

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What a bowl of spaghetti haha.

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Still looking like I’ll be able to land all the non power signals on the four inner layers though.

Power is easy enough on the upper and lower. But 5v remains a question mark. Will have a clearer picture of what can be done once connections are landed. May end up using inner layers for gnd and outer for vcc3 and vcc5

Of course, once landed they need to be optimized (position tweaked, routing tweaked) which will take a very long time.

Taking a look at a inner layer, it looks like the plan for using each layer for only a specific direction of routing has allowed ground planes to propitiate. Which is what I was hoping for and should help signaling.

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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 238 of 1198, by feipoa

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Don't you want to include the overhang lip before optimising traces? I didn't see the overhang in those images, which would contain VRM, trimmer, 3-pin header, and maybe a tantalum, space permitting. VRM, trimmer, and 3-pin header would all be through-hole, while the caps and resistor SMD.

Plan your life wisely, you'll be dead before you know it.

Reply 239 of 1198, by Sphere478

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feipoa wrote on 2022-09-12, 07:21:

Don't you want to include the overhang lip before optimising traces? I didn't see the overhang in those images, which would contain VRM, trimmer, 3-pin header, and maybe a tantalum, space permitting. VRM, trimmer, and 3-pin header would all be through-hole, while the caps and resistor SMD.

Haven’t gotten there yet. There is so much more work left, this isn’t even close to done.

Had to make sure that it was even possible to land all the connections on 4 inner layers.

And update: it is.

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The next thing I want to do is go through and tweak the routing of these traces.

I’m hoping between the four inner layers to have enough of a ground connection there to use it as a single stitched together gnd power plane.

Adding a overhang is easy, just gotta change the edge cuts. And tap into the power planes for the vrm.

Right now I have vcc5 on blue, vcc3 on red and gnd on all inner layers. These are floods so they go basically everywhere so long as there is a path from another part of the flood on that layer or a connection to a pad with that designation. On the top and bottom layers I should be able to extend the gnd plane to the center to act as a emi shield for signals passing through there. There should be enough around the pins/perimeter to carry the load. At least this is the current idea. Does this all seem okay so far?

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)