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VT83C461 VL-IDE controller PIO timings setting

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First post, by vt83c461

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There is a VT83C461 VLB IDE controller chip on a FIC 486-VIP-IO motherboard. It requires software initialization to enable faster than PIO-0 transfer mode and the system BIOS doesn't have it included.

There is a device driver VIAIDE.SYS available for that purpose at http://mpolibbs.steptail.com/drivers_1/HD/OHJ … /ATID/VT83C461/ but for some reason it doesn't seem to want to recognize some CF card vendor strings correctly and apply the cycle time configured with VTSETUP.EXE. Moreover the whole driver is pretty much useless and takes 12KB of memory, seemingly replacing the bios routines with it's own. The timings stay active after reboot without loading the driver and Win3x 32-bit disk access works with SEG32BIT.386 driver and SPEEDSYS still shows comparable speed to with VIA driver loaded around ~4-8MB/sec under DOS.

Would someone be able to help disassemble the driver and figure out the initialization routine and create a simple tool for setting the timings. It could then also be added to XT-IDE BIOS and maybe OS/2 DANIS506 driver and Win95 driver, which currently can't be worked out at all, because VIA drivers don't seem to work at all with OS/2 Warp 4 or Windows 95 and only way to keep the faster timings is by booting to DOS, loading the driver and then soft rebooting to OS/2 or Windows 95.

Reply 1 of 3, by mkarcher

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I do stuff like that as afternoon snack. Let me peek a look at it, although it's not yet afternoon here. BTW: Your mpoli mirror link doesn't serve the actual files right now, and the original is unreachable 🙁 🙁 . I got viaide.sys from https://web.archive.org/web/20131215233504/ht … /ATID/VT83C461/

Reply 2 of 3, by mkarcher

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OK, here you are.

The VT83C461 is configured using I/O ports B4, B8 and BC (8-bit access).

  • Port B4 used to enable/disable the other ports: 03 -> allow configuration, 04 -> block configuration.
  • B8 is used to select a register
  • BC is used to read/write the selected register

The registers (as far as I can guess/tell from the driver) work like this

  • Index 1: 01h -> "basic operation" (before initialization complete), 31h -> "full operation". I suppose, these two bits enable prefetching and write buffering to optimize VL performance.
  • Index 2: Block mode control. Drive 0: low nibble, Drive 1: high nibble. 0F for block sizes 1,2 or 4; 0E for block size 8, 0D for block size 16, ..., 0A for block size 128. Likely used to avoid prefetching over block ends.
  • Index 3: Drive 0 (master) timing A (likely for data access): low 4 bits: active time in VL clocks (-1), so range is 1..16, high 4 bits: recovery time in VL clocks (-1).
  • Index 4: Drive 0 timing B (likely for non-data register access): works like index 3, initialized the same by the driver
  • Index 7: After writing FF, you read back 03 - used to detect the presence of the chip. Possibly fixed at 03. Possibly bits 0/1 are RW.
  • Index 8: Drive 1 (slave) timing A: Like index 3, but for drive 1.
  • Index 9: Drive 1 timing B: Like index 4, but for drive 1.
  • Index F: Unknown purpose. Always written 10h before timings are set.

That's all we can learn about the configuration of the VIA IDE controller by reverse engineering VIAIDE.SYS

Reply 3 of 3, by vt83c461

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mkarcher wrote on 2022-11-19, 10:35:
OK, here you are. […]
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OK, here you are.

The VT83C461 is configured using I/O ports B4, B8 and BC (8-bit access).

  • Port B4 used to enable/disable the other ports: 03 -> allow configuration, 04 -> block configuration.
  • B8 is used to select a register
  • BC is used to read/write the selected register

The registers (as far as I can guess/tell from the driver) work like this

  • Index 1: 01h -> "basic operation" (before initialization complete), 31h -> "full operation". I suppose, these two bits enable prefetching and write buffering to optimize VL performance.
  • Index 2: Block mode control. Drive 0: low nibble, Drive 1: high nibble. 0F for block sizes 1,2 or 4; 0E for block size 8, 0D for block size 16, ..., 0A for block size 128. Likely used to avoid prefetching over block ends.
  • Index 3: Drive 0 (master) timing A (likely for data access): low 4 bits: active time in VL clocks (-1), so range is 1..16, high 4 bits: recovery time in VL clocks (-1).
  • Index 4: Drive 0 timing B (likely for non-data register access): works like index 3, initialized the same by the driver
  • Index 7: After writing FF, you read back 03 - used to detect the presence of the chip. Possibly fixed at 03. Possibly bits 0/1 are RW.
  • Index 8: Drive 1 (slave) timing A: Like index 3, but for drive 1.
  • Index 9: Drive 1 timing B: Like index 4, but for drive 1.
  • Index F: Unknown purpose. Always written 10h before timings are set.

That's all we can learn about the configuration of the VIA IDE controller by reverse engineering VIAIDE.SYS

That was quick. I tested it by poking the registers with debug.exe and it all seems to work. Thank you very much.

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