I attach a picture of my cache configuration, doing the math it should be 256KB, but I see unused pins on 4 sockets... what would they be for?

My guess is that you could probably get to 256 with 5 chips and in that case you would use those pins and leave the other 4 sockets across from them empty.

Btw, are those installed in the correct pins? Seems odd that the notch wouldn’t be lined up

Sphere478 wrote on 2022-11-21, 09:19:

My guess is that you could probably get to 256 with 5 chips and in that case you would use those pins and leave the other 4 sockets across from them empty.

Btw, are those installed in the correct pins? Seems odd that the notch wouldn’t be lined up

If the are wrong system can't see the 256.. in my opinion.

capacita della cache 256 is right there in the middle

rasz_pl wrote on 2022-11-21, 09:54:

capacita della cache 256 is right there in the middle

Yes i know that the system see all 256KB. i do not know whats the empty pin on the socket are for.

and what to say instead of the topic mainly covered in the post?

Must be right then 😀 just checking!

I think the extra pins are for what I talked about. Doing 256k with denser chips. I’m betting that address lines are only provided for up to 256k

Someone who knows more about this will chime in soon and confirm or dispel.

AlessandroB wrote on 2022-11-21, 08:45:

Wanting to expand the view a little, for example my system (IBM PC330 DX4) was born as one of the last 486 products from IBM and can have 128 or 256KB of cache, up to 128MB of RAM (as suggested by a user not entirely covered by the cache), it's a VLB system but you can change the riserboard with a PCI one (finding one is very difficult), the possible CPUs range from SX20 to DX4, POD83 and Cyrix 5x86 also work, strangely the AMD 5x86 doesn't, but not I think it changes the meaning of the post.

Well, the rule for cacheable area is not strict to all systems.
Some systems may have space for an extra TAG ram to enhance cache capabilities. If such a module extends the number of address bits the cacheable area may raise significant.
Basically these motherboards do not play in the consumer class, but I can imagine that some IBM or DELL workstation or server boards may have extra TAG sockets.

Sphere478 wrote on 2022-11-21, 09:19:

My guess is that you could probably get to 256 with 5 chips and in that case you would use those pins and leave the other 4 sockets across from them empty.

Yeah. The chips currently installed have 32kiloaddresses and 8 bits each. They are forming two banks of 32 kiloaddresses and 32 bits each. The 486 processor needs 32 bits at once for full performance, that's why each cache bank is 32 bits wide. 32 kiloaddresses of 32 bits (4 bytes) equals 128 kilobytes. All usual 486 chipsets use bank interleaving for L2 cache, that means that during a burst, the banks get accessed one after the other so that the first bank can prepare for the third access while the second bank still delivers the second word.

The alternate configuration would be 4 chips of 64 kiloaddresses, each containing 8 bits. This configuration also provides 256kb of cache, but only uses a single bank. This can be slower because there is no bank interleaving, but at the same time, it is cheaper because at the time 64K x 8 chips were common, the price was less than that of two 32K x 8 chips. The 64K x 8 chips have 32 pins and occupy the socket for the primary bank completely; the 32K x 8 chips only have 28 pins. The secondary bank is not prepared for 64K x 8 chips, so you can't install 512KB of cache using 8 64K x 8 chips.

Sphere478 wrote on 2022-11-21, 09:19:

Btw, are those installed in the correct pins? Seems odd that the notch wouldn’t be lined up

That's the correct installation of 28-pin SRAM chips in 32-pin sockets. The 4 empty pins always need to be at the end with the notch.

mkarcher wrote on 2022-11-21, 14:22:

Yeah. The chips currently installed have 32kiloaddresses and 8 bits each. They are forming two banks of 32 kiloaddresses and 32 […]
Show full quote

Sphere478 wrote on 2022-11-21, 09:19:

My guess is that you could probably get to 256 with 5 chips and in that case you would use those pins and leave the other 4 sockets across from them empty.

Yeah. The chips currently installed have 32kiloaddresses and 8 bits each. They are forming two banks of 32 kiloaddresses and 32 bits each. The 486 processor needs 32 bits at once for full performance, that's why each cache bank is 32 bits wide. 32 kiloaddresses of 32 bits (4 bytes) equals 128 kilobytes. All usual 486 chipsets use bank interleaving for L2 cache, that means that during a burst, the banks get accessed one after the other so that the first bank can prepare for the third access while the second bank still delivers the second word.

The alternate configuration would be 4 chips of 64 kiloaddresses, each containing 8 bits. This configuration also provides 256kb of cache, but only uses a single bank. This can be slower because there is no bank interleaving, but at the same time, it is cheaper because at the time 64K x 8 chips were common, the price was less than that of two 32K x 8 chips. The 64K x 8 chips have 32 pins and occupy the socket for the primary bank completely; the 32K x 8 chips only have 28 pins. The secondary bank is not prepared for 64K x 8 chips, so you can't install 512KB of cache using 8 64K x 8 chips.

Sphere478 wrote on 2022-11-21, 09:19:

Btw, are those installed in the correct pins? Seems odd that the notch wouldn’t be lined up

That's the correct installation of 28-pin SRAM chips in 32-pin sockets. The 4 empty pins always need to be at the end with the notch.

WOW! What a detailed explanation, thank you! what do you think instead of the amount of memory and the considerations I made in the first post?

AlessandroB wrote on 2022-11-21, 15:01:

WOW! What a detailed explanation, thank you! what do you think instead of the amount of memory and the considerations I made in the first post?

128KB of cache is an uncommon cache size on last-gen boards. 256KB was the entry-level configuration by then. 512KB/1024KB were uncommon expensive options. So I would go with 256KB cache as "default configuration". For PCI-based systems with PCI at 33MHz, you do not need to consider FSB40 or FSB50, and last-gen boards manage to get 2-1-1-1 burst at FSB33 from single bank cache. 2-1-1-1 burst means that data can be copied from the L2 cache to the L1 cache in 5 clocks, that's the fasted speed the 486 has to offer. If you are interested in overclocking, and don't care about 40MHz PCI clock on a 5x86-160 (4x40MHz), you should prefer boards that offer two banks of cache.

The amount of RAM depends heavily on what you want to do with the system. For DOS games, 16MB should be enough. Surfing the Web with something like Netscape 6 or Internet Explorer 6 can profit from more memory, especially on complicated sites. If you want to edit documents with high-resolution images in them using Microsoft Word, more than 16MB might also come in very handy. Most Windows games that run at an acceptable speed on a socket 3 system will not require more than 32MB, so you are likely fine to go with 32MB for gaming. On the other hand, if you want to rebuilt your office's file email and database server using Windows NT, you might want to have 64MB or even more to be used as cache for disk files and database indices.

so, even with a DX4/POD/5x86 32MB are more and more than enough? With a POD you can use win95 for example, is not better to have more than 32Mb? correct me if i'm wrong

You should avoid using more than is cachable. On socket 5/7 a common issue was a max cachable of 64mb this was avoided by using a chipset cache size, bios, and tag configuration that supported more. Or a k6-2+\3\3+

What the cachable limit on your board is I am unsure.but it is based on cache, tag, and chipset capabilities usually

Sometimes it is worth it to exceed the cachable limit if you truly need that much ram, it is better than not having it. But if you are able to reasonably operate under the cachable limit you should do so.

My POD 83 system runs pretty well with 32mb and 256k I run windows 95

Re: Gateway 2000 overdrive build

Based on the sockets I don’t think your board supports more than 256k or maybe 384k? (Is that possible) of cache.

Thoughts mkarcher?

Sphere478 wrote on 2022-11-21, 15:55:

You should avoid using more than is cachable. On socket 5/7 a common issue was a max cachable of 64mb this was avoided by using […]
Show full quote

You should avoid using more than is cachable. On socket 5/7 a common issue was a max cachable of 64mb this was avoided by using a chipset cache size, bios, and tag configuration that supported more. Or a k6-2+\3\3+

What the cachable limit on your board is I am unsure.but it is based on cache, tag, and chipset capabilities usually

Sometimes it is worth it to exceed the cachable limit if you truly need that much ram, it is better than not having it. But if you are able to reasonably operate under the cachable limit you should do so.

My POD 83 system runs pretty well with 32mb and 256k I run windows 95

Re: Gateway 2000 overdrive build

Based on the sockets I don’t think your board supports more than 256k or maybe 384k? (Is that possible) of cache.

Thoughts mkarcher?

The concept is not only "ram needed" but also the maximum ram i can feed, related to the cached issue, for example, after this IBM i will play with cache/ram on (always IBM) P60 and P200 with HX chipset. If my DX4 support (cached) 128Mb i will install, also because i will use POD83 and so on.

Just to make a preview... my P60 have only 256KB cache non upgradable and the HX... will be more tricky with to coast module.