Nice! Routing and nets are gonna be fun haha

Might have some time to play with this if it is wanted.

But, how will we assemble these? Does anyone have a plan? Or the skills for that matter?

I have one of these btw can use it as a reference if we have questions.

In theory, stencil the exact right amount of grey goop on it, apply heat and it beads up nice on the pads... yay surface tension.

Netlist done...
It seems there's not much crossings...

>Sphere478
Do you have some better photos?

Autorouter? No no, no way...

Here ya go

Thx, I found also some good photos of a different adapter here:
https://www.x86-guide.net/Xhoba/en/collection … 550-bottom.html

Yeah, it seems there were a few designs.

I wonder if maybe flipping the side that the chip is on might be a good idea as to expose the core to the top so that a proper heat spreader could be used.

You could leave a hole in the middle to read the chip.

From recent experience with a Pentium pre-MMX in this package, the core is extremely fragile, it would not survive a heatsink I think. I left scratches on it just trying to clean thermal paste with plastic tweezers: Re: Toshiba Satellite 200CDS 810 - troubleshooting and general info (KBC error - trying to solve, help needed)

Now it seems the hive is routable (~50 nets remains), but it would route better if the chip can be rotated by 45deg but then very little space left between chip's and PGA pins. I manage to route in 2 layers while preserving 1 layer for full GND and 1 layer will be for VCC2 and VCC3 polygons (will be optimized at the end). Also may add some 0603 caps somewhere if some space left...

I vote to put caps in same place as pmmx.

See my processor imposter project for spacing/location/edge cuts of pmmx caps

Wow, new Golden tigers would be amazing

You could probably cut and file a piece of copper and solder it to the back of the pcb like a pmmx also.

Btw, you may find copying and pasting the flood polygons from my projects useful. The voltage interposer tweaker probably has a polygon of interest

If in doing this you run into anything suggesting that intel didn’t run the smp pins on the interposer and that they actually exist on the film chip please speak up and do route them!

Tillamook SMP and multiplier unlocking investigation thread.

Soldering TCP by hand directly is impossible due to ultra delicate leads. You need to prepare the pads with solder including the center part for cooling *correct amount!* with solder (by heating them) washable flux, clean again, then lay the TCP atop with some washable flux and "bake" or carefully heat with hot air taking care not to blow processor TCP off. Then you cannot clean mechanically. Clean (no-touch) with ultrasonic method and alcohol in small closed container in water bath.

Honestly get a BGA pentium (available in 166 and 266. Both are 2.0V) instead and put it on the BGA interposer. Enbedded BGA pentium is full featured CPU minus few pins that is needed for multi-processor so this does not matter, Yes I looked at the datasheet carefully.

Reusing TCP, I don't know. They are easy to get but already on the daughterboards.

Cheers,

Oh that’s a fun idea, bga pentium is definitely doable

What "smp pins" do you mean?
I only found that some pins on PGA, like e.g. those in Dual Processor Private Interface group: PBGNT#, PBREQ#, PHIT#, PHITM# doesn't have it's counterparts on SMD package. Also it's mentioned as
"Table 1. Signals Removed in Mobile Pentium ® Processor with MMX™ Technology 200/233 MHz" so I don't know where to route them when they are not on pins.
I'm done with all signal nets, just need to optimize power planes. Of course I need planes customized for my design to reach all power vias so I cannot simply reuse them from other design. But it's easy compared to routing that was a bit hell (effectively using only 2 layers because I left one for GND and second for 2 VCCs).

I also need to finish my 72-pin 36bit SIMM module design before sendinng whole batch to JLC...

RayeR wrote on 2022-12-05, 14:34:

What "smp pins" do you mean? I only found that some pins on PGA, like e.g. those in Dual Processor Private Interface group: PBG […]
Show full quote

What "smp pins" do you mean?
I only found that some pins on PGA, like e.g. those in Dual Processor Private Interface group: PBGNT#, PBREQ#, PHIT#, PHITM# doesn't have it's counterparts on SMD package. Also it's mentioned as
"Table 1. Signals Removed in Mobile Pentium ® Processor with MMX™ Technology 200/233 MHz" so I don't know where to route them when they are not on pins.
I'm done with all signal nets, just need to optimize power planes. Of course I need planes customized for my design to reach all power vias so I cannot simply reuse them from other design. But it's easy compared to routing that was a bit hell (effectively using only 2 layers because I left one for GND and second for 2 VCCs).

I also need to finish my 72-pin 36bit SIMM module design before sendinng whole batch to JLC...

https://www.pchardwarelinks.com/586pin.htm

See intel specific at bottom many of those are related to smp

These BGA is intended for embedded use but it is really regular pentium mmx without SMP pins and will work on motherboards. Same with TCP as you found.

Cheers,

Sphere478 wrote on 2022-12-05, 18:42:

https://www.pchardwarelinks.com/586pin.htm
See intel specific at bottom many of those are related to smp

I see, but those pins are not used on SMD CPU, as already pentiumspeed noted, so I don't care about them.

I was just asking if you happened to discover them, let me know. Because it has been a project of mine to try and dual some tillamooks.

Probably won’t happen but just in case you discover some suspicious unlabeled pins on the tcp or bga 😀