the v in and v out are already connected with three vias to ground each and their other ends are direct to plane and direct to power pin of regulator.

can you draw on here what you want changed?

Internally there are four ground planes between red and blue layers (not shown) red and blue are top and bottom and are 5v and 3.3v

pentiumspeed wrote on 2022-12-05, 20:03:

I didn't say lower. I meant lower ESR is better.

while its NOT for LDOs, we have been over this 4 pages ago 😀

pentiumspeed wrote on 2022-12-05, 20:03:

MLCC capacitors have this and can output higher current spikes which is what you did. Tantalums is good for bulk capacitance but needs so many to get desired lower ESR goal

LDOs require high esr ...

pentiumspeed wrote on 2022-12-05, 20:30:

I can see the problem. Not enough vias for power plane and ground.

3W cpu ...

pentiumspeed wrote on 2022-12-05, 20:30:

This is typical design of APU with this capacitors and many vias look like, I know this is extreme.
https://guide-images.cdn.ifixit.com/igi/S5Uno … 5g5uVSO6HM.huge
https://guide-images.cdn.ifixit.com/igi/QiyYG … B2mVAtCcxy.huge

150 W APU ...

^Good point about the power difference.

But if there is a way to improve resistance, I am listening.

impedance, one thing you can incorporate is routing Vcc3 out of LDO first to Cout, and only from under Cout it goes further (like the wire mod I suggested earlier)
You could probably do as wide Cout footprint as possible so user can solder two caps next to each other on same pad, maybe even second Cout footprint on the other side if feipoa determines more than one cap are needed (I dont think thats going to be the case with proper decoupling now).

vcc3 is in a weird place to try and do that, but it may be possible. we will loose current carrying cross section for sure though.

I see a few ways to add one or two more vias to the cin and cout gnd but it's gonna again cut current carrying cross section and look weird. waiting to hear if it is really needed. I was able to make the 5v trace to the regulator larger no problem.

🤔

Whatcha think?

I’ve been tweaking this for a few hours now. The component overhang is now smaller.

Beforehand I tried to add two caps, clearance wasn’t having it so decided to just make the overhang smaller. Moved the pin header in a little and have been re ordering traces.

Vcc pin off the regulator is now passing directly to the vout cap before entering the power plane.

Oh dang, getting pretty creative here. I think you all are going to like this,

I managed to not only make it smaller, but I managed to fit two Cout tantalums on the pcb. And the paths of them take them evenly to both sides of the overhang. 1/3 way across and 2/3 way across.

The way I did it though, I don’t think using one will be a good option. Two must be used.

Much better.

Now you know how complicated this is now in designing a successful PCB design that works against budget imposed by not very knowledgeable business people.

Cheers,

Haha, I tried to warn feiopa we were in for a prototyping adventure.

Okay,
Here we go. This is really getting quite refined..

The vout is now passing to the interposer directly through the dual Cout pads. Freakin perfect!

This new design I bet is a lot cleaner on power.

Populate all three tantrums, and all of the decoupling spots and I bet we surpass the oem unit in power quality.

I also changed the j1 pads to resistor pads so they hold less solder, as well, I pulled solder mask clearance all the way back to the pads on several of the pads. Not sure why they weren’t 0 clearance in the first place.

Do you all think that the 5v Cin cap needs to have the current channeled through the pad like cout? Or is it okay like is?

Thoughts on this added ground plane? (Bottom of pcb)

The 5 v plane is basically a ring because of the traces that had to be on blue layer in middle.

5v being higher voltage will be lower current than 3.3v plane. Most narrow point is lower left. Would have to abandon that ground pin on this layer and re route a10 to make wider there.

rasz_pl,
Yes I have several images showing the 5V line, some pages back. It will be the blue coloured line. I can connect CH2 again for continued testing, just it was creating more effort connecting/disconnecting. 5V was clean.

as I kept repeating. cant just plop caps anywhere, speaking of which:

lol, clearly. The central cap regions weren't my idea and I didn't think it would matter much for 386 class hardware. The oscillations didn't happen with an ordinary PGA132 SXL, so I think some aspect of the PCB is amplifying them more than expected. The next time I have my BL3 interposer or my Evergreen SXL2-66 accessible, I will try to remember to update this thread with the voltage noise. It would make for an interesting comparison to remove the few ceramics on the BL3 and Evergreen interposers to measure the waveform. Even with the Improve It + Gainbery, it would be intersting to slowly remove the bottom caps to see how it changes the waveform and how many of the caps were minimally necessary.

ignore those footprints in the middle, if you want to add bulk caps solder them on top of Cout

Yes, that is my feeling, but I'm still going to double check.

I would feel a lot more comfortable if 5V fill was shrank away around those caps

I think sphere is adding silkscreen over the that section of the 5V plane. However, since the 0805 caps fit just snug (at least the particular pieces I have on hand), it is just as simple to raise the cap up 0.5 mm from the PCB, then solder it.

pentiumspeed wrote on 2022-12-05, 18:59:

That is correct way to deal with! I said MLCC capacitors all along, But why is the 8 capacitors not populated in the center area, preferably large MLCC capacitors?

Probably because you were looking primarily at select photos and glancing thru the text. I already tried populating the centre region with a total of 6 MLCC caps. It did not help whatsoever. The solution to the low frequency oscillator came from rasz_pl. The idea came to me briefly, but I quickly brushed it off thinking the pins weren't accessible and felt if the centre region did nothing, maybe closer caps wouldn't do much either. I even went into the solder job thinking 'what a waste of time'. haha...

Does anyone know what aspect of the PCB design may be amplifying this low freq waveform? Some kind of power or ground loop amplification? Is it just due to insufficient via counts and thin ground/power planes like pentiumspeed alluded to? I already showed that connecting VRM OUT to COUT before the VCC3 plane didn't reduce the low freq. noise.

I understand there are more than one model of this cpu?

There is only one model of relevant interest. Would anyone want to run 50 MHz chip in this interposer, and the uncommon variant at that?

As you can see in gerber view silk isn’t covering pad in final CAD files

Is that image with the white rectangulars silkscreen? If so, it sure looks like it is covering the through-hole, which wants solder. EDIT: Looks like you provided another image later showing the through-hole contact. I'd personally turn those rectangles into ovals. The rectangles don't look as nice. Personally, I'd only add silkscreen to the 10 locations I identified. More symmetry, more pleasing to the eye. W don't know if those extra 11 Vcc-Gnd locations provide any improvement. If they aren't necessary, let's save people some effort with assembly. If it helps, I can solder caps on to those extra 11 locations to see if it does anything to the waveform.

Is there enough room for four caps near the regulator?

I think you are getting ahead of yourself. It is unlikely that we will need more than one Cin/Cout near the VRM. We also don't need to use these giant tantalums. Let's wait for more testing around there before adding more pads for more caps.

rasz_pl wrote on 2022-12-05, 21:06:

pentiumspeed wrote on 2022-12-05, 20:03:

I didn't say lower. I meant lower ESR is better.

while its NOT for LDOs, we have been over this 4 pages ago :)

That was my immediate thought too.
But for the direct-pin cap soldering, what would happen if I put ten 100nF 0805 tantalums to the pins instead of ceramic? Unfortunatley, I only have 10 uF tantalums on hand in 0805.

Sphere478 wrote on 2022-12-05, 23:38:

...Moved the pin header in a little and have been re ordering traces.

Be careful, don't go any further than I stated previously. With the CPU I currently have installed, I think it was 0.7 mm MAX. However, not all heatsinks are precision placed. Because of this, 0.5 mm is a safer maximum. Also, the trimmer is already touching the heatsink. Did you move that too? I hope not.

Sphere478 wrote on 2022-12-06, 00:21:

Oh dang, getting pretty creative here. I think you all are going to like this,

I managed to not only make it smaller, but I managed to fit two Cout tantalums on the pcb. And the paths of them take them evenly to both sides of the overhang. 1/3 way across and 2/3 way across.
The way I did it though, I don’t think using one will be a good option. Two must be used.

I don't recommend doing this at this juncture. The 2312 tantalum is rather tall and putting it on the bottom greatly increase the chance of an obstruction bumping into it. If you've delt with a lot of upgrade interposers on a 386, you'd understand. With just the two motherboards I've tested the current interposer on, I have a pin header just rubbing up against the unit, and on another board, I had a tantalum nudge the bottom of the interposer. IFF it is determined that more than one tantalum is necessary for Cout (I doubt it will be), it would be better to use two smaller tantalums on the top in place of the 2312. Trust me on this.

Sphere478 wrote on 2022-12-06, 01:42:

Haha, I tried to warn feiopa we were in for a prototyping adventure.

I had no inclination one way or the other. If it happens fine, if not save time. I think 99% of people who received the existing alpha would not have checked the waveform at all and said all is good after 10 min. of testing. Due to the cost involved with 6-layer boards, I will not be ordering more to test. If someone else orders some of the later revision and wants to send me two boards to test, I'll be happy to check them against alpha1.

Since we are doing revisions right now, I think swapping the sides the Cin and Cout are on would be neater. In my opinion, Cout should be near the voltage-set trimmer, rather than the other side of the VRM.

Thoughts on this added ground plane? (Bottom of pcb)

Did you add more vias to/from the ground/Vcc3/Vcc5 planes per a users recommendation?

Do you all think that the 5v Cin cap needs to have the current channeled through the pad like cout? Or is it okay like is?

I don't think so, provided Cout is right at the VRM's input. Rasz_pl may have more input on this though.

5v being higher voltage will be lower current than 3.3v plane.

I'm not familiar with PCB design (bastards didn't have it as part of my late 90's EE curriculum), but is it not total power that matters, not current alone?

rasz_pl, attached is Vin (blue, 5V) and Vout (yellow, 4V) plotted on the latest design with:

10x 100 nF 0805 ceramic caps at PGA pins,
22 uF, 470 nF, 150 nF, 220 nF tantalum in centre region
1x 10 uF 1206 ceramic at Cin VRM
1x 10 uF 2313 tantalum at Cout VRM

Variable voltage DC power line (4.0 V) going straight to Cout VRM

Scope is showing a larger width of 10.0 ms to try and catch more noise peaks, but my standard of 250 us looks similar. I took a few measurements to arrive at an average noise of Vin vs. Vout.

Vin | Vout
64 mV | 88 mV
72 mV | 88 mV
64 mV | 96 mV
56 mV | 80 mV
72 mV | 80 mV
64 mV | 72 mV

Vin average = 65.3 mV
Vout average = 84.0 mV

The noise on Vin, that is, the 5V line from motherboard going to the interposer is an average of 18.7 mV less than the noise on Vout.

Okay, just to repeat this, there are ground planes everywhere on this interposer. All six layers in fact have at least one plane and I did my best to connect them. The idea was to try and absorb as much stray EMI as possible. We may see that EMI as ripple on the ground plane. If so, that was kinda the whole idea. But of course we want to try and minimize it in both places.

Anyway, this is my logic. Maybe I am way off. I do the best I can 😀

I am trying to silk everything I fear may solder bridge.

Please list ALL variants of cpus that will work. I wish to add this to the silk screen.

Silk screen covering pads in 3d view. Look at green rectangles with circles that is the cad output for the gerber. There is a hole not shown on 3d view. Another user said this was okay, and they appear to be correct

To test caps in not all locations idea you will have to probe the power plane in the empty spaces. If you want to test this and can prove that the other caps do the job I’ll feel better about removing the OPTIONAL silk locations. But it seems like a bad idea to remove the feature. It is after all hidden under the cpu.

The very problem we are fixing with this honestly ridiculous impedance issue basically proves that we should use all available spaces for a better local waveform.

I only moved smd parts and the pin header. I believe we are okay. The trim pot is unchanged. The tantalums are unchanged the regulator is unchanged

Okay I’ll wait to hear about the tantrums. But i got a really nice config figured out, I think it is better.

Clearance issue with tantrum: 🤔 yeah. I hear you. A socket stack can solve. But I agree I want it to clear as much as possible without a socket.

The dual cout is really nice, look at it. It’s evenly distributing to the plane.

Currently cout is on top both spaces
And
Cin is on bottom. This makes sense because of where the 3v and 5v planes are located.

More vias:
I moved some parts in such a way that vias weren’t required at all in some places now. With the power levels we are at I think this is already overkill the way it is, but if anyone has specific suggestions of locations to add more vias let me know. (With a picture please 😀 )

The ground plane has vias everywhere… literally everywhere.

The power planes are only on one layer each so vias to the components they go to are the only vias that are required and the number is dependent on the load those devices use. As it stands the latest revision splits cout into two caps with three vias each on ground, positive is direct to plane. I increased the ground trace width to these vias. And the total number of vias has doubled.

Current:
As far as I know, voltage needs spark gap and amps need cross section and cooling. Amps are what induce signals in near by wires through inductance voltage, by leakage. We honestly aren’t dealing with much of amps or volts here. But the 5v plane definitely doesn’t cary as much current as the 3.3v plane.

Here is my thought;

We should do this last version but not until Feiopa does more tests.

I vote Feiopa and I have done a lot of work here so a third interested party should order some pcbs when we are ready to Feiopa’s address and Feiopa could assemble and test the new design. I think that person should in return get back at least one assembled unit? 😀 sound fair? Whatcha think Feiopa?

All done replying 😀 (thousand edits 🤣)

Yeah those caps on the pins really did the trick didn’t they?

Can you do tests without center region? I have removed it from the design entirely.

I rounded em and made em smaller. More rounded or is this okay? Did you have a different shape in mind?

The pads are shown covered but won’t be

You are getting too far ahead of my testing speed. It could result in time wasted on your end, but if you have plenty of time, no issue.

The exact SXL2 model numbers are listed in the datasheet and were talked about, perhaps 10 pages ago. Any PGA-168 SXL or SXL2 should work on this interposer. I think adding the exact model numbers could cause some confusion because the ceramic surface of SXL PGA168 chips do not have the model number listed (at least not on any of mine). Any PGA-168 SXL/SXL2 will function in this interposer. Even the motherboard I'm testing on right now, I've had to smash the tantalum flat to make the interposer fit. Some people with collector grade boards may not want to smash their tantalum, or they may have something else like a jumper in the way. It happens all the time.

Keep in mind that just because silkscreen might not be present around those OPTIONAL PGA ceramics, it doesn't mean others cannot install them. But to have the silkscreen and not install the ceramics will look incomplete. 23 ceramics seems way overkill, but I will test for it. If they brings the noise down to like 20 mV, then I'm onboard with you - it is worth the lack of symmetry. But if it does absolutely nothing...

Personally, I'd round them out a bit more. I was also wondering if we should have the mask extend past the vias like that. I cannot decide. Don't the masks only need to go to the mid-section of the via?

I haven't had time to remove the centre caps yet. I will first remove the centra caps, then snap a waveform. Then add the 13 extra caps, snap a waveform. Then add the LP regulator, then swap for MIC regulator. LP regulator cannot screw onto the heatsink, is this important? I think it will look better screwed in and should dissapate the thiny amount of heat better. But the heat is so low that it is more of an operation of optics.

Regardless of the test results, if you are insistant on having a cap on the bottom surface, you should switch it to some flat pack ceramic capacitor. Cin need not be a tantalum, we just went with double tantalums previously for symmetry around the VRM. Unfortunately, even the 0805 ceramics I have that are 10 uF are probably 2x thicker than 1/4 W 0805 resistors. Maybe there are some that can be really thin like the 1/4W SMD resistors. It is better to go wider rather than taller w.r.t. the SMD package type.

Squared or round🤔

Here is what final product will look like:

hmm, if there's going to be a democratic vote, put me in for rounded. But also consider adding a wildcard - a 3rd option which only goes to the centre of both vias, squared ends with a tiny hint of rounding (like shown on the rectangulars above). haha.