So far the only objective benchmarks suggested are the video tests from Check It and Landmark, which seem oriented towards text […]
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So far the only objective benchmarks suggested are the video tests from Check It and Landmark, which seem oriented towards text mode performance. Any others out there?
I don't think EGA 4bpp has to be any slower than CGA 2bpp, because one of the big features of EGA graphics is the capability to modify all four colour planes with a single 8-bit memory write. The main performance limitation is the wait states that the EGA imposes on the CPU when reading/writing video RAM.
The original EGA chipset from IBM (along with the first clone EGA chipset from Chips & Technologies) clocks the video RAM at the dot clock frequency, which is 14.318Mhz for the 320x200 and 640x200 modes. The chipset sequencer coordinates the CRT and CPU accesses to video RAM. Over the course of 32 clock cycles the sequencer provides 5 opportunities to access the video RAM. The CRT needs 2 out of 5 accesses in 320 pixel modes and 4 out of 5 accesses in 640 pixel modes. When the CPU wants to read/write to video RAM, the video chipset inserts wait states until an access opportunity becomes available. (This will be quite a few wait states in the 640 pixel modes!)
So I think on these early EGA cards, the video RAM would actually be *faster* in 640x350 mode (since it uses a 16.257Mhz clock) as compared to 640x200 mode (which is using the standard 14.318Mhz clock). There's a "bandwidth" bit in the SR01 register that determines whether the CPU gets 1 access or 3 accesses during each 32 cycle group. I wonder what happens if you program the sequencer to give the CPU 3 accesses in a 640 pixel mode (which should starve the CRT of its required accesses). It might be safe to do so during the vertical blanking, providing a brief window of high performance access to the video RAM...
Anyhow, at some point the video chipsets began to incorporate a FIFO buffer, so that the CPU writes into the buffer and can be released immediately without any wait states, and also switched to clocking the video RAM with a faster clock that was decoupled from the video dot clock. Did any EGA chipsets use these techniques? The early VGA chipsets used essentially the same design as the original EGA, adding a whole bunch of wait states to synchronize the CPU writes with the gaps in the CRT reads.