Since in the other thread there is a reservation for future use, I need to repeat the question here, but I've modified it a bit to hopefully fit your needs and to get an answer now.

As you might know the first Am486 were clones of the i486, how can you detect the difference?
Just after a lawsuit AMD had to make a clean-house developement, and that was the difference between AMD DX4 V8T and NV8T.
Are there any differences that could be detected?

And is there a way to get the contents of what is in the DX register after invoking RESET?

Reserved for future use.

Disruptor wrote on 2023-03-31, 18:40:

And is there a way to get the contents of what is in the DX register after invoking RESET?

Some BIOSes stash it in a CMOS register, and perhaps even provide an INT 15h or such to retrieve it, but I don't think it's standardized at all.

AFAIK the first Intel 486 CPU to support a write-back cache is the DX2-66 SX955 CPUID 0436, though it may be my DX2-66 SX807 CPUID 0436, which also supports write-back ,is different to the CPUID 0435 specified in https://www.cpu-world.com/sspec/SX/SX807.html and I suspect predates the SX955.

Does anyone know why my SX807 is different to the one on cpu-world please?

red-ray wrote on 2023-04-03, 07:54:

though it may be my DX2-66 SX807 CPUID 0436, which also supports write-back

Are you sure it supports L1WB? As far as I know, "&E" means SMM and CPUID (the "SL enhanced" core), and "&EW" means L1WB support. The picture you link shows "&E".

red-ray wrote on 2023-04-03, 07:54:

is different to the CPUID 0435 specified in https://www.cpu-world.com/sspec/SX/SX807.html and I suspect predates the SX955.

The SX955 shown in CPUworld is an &EW processor, so that one in fact should support L1WB. I used to think that the S-Spec numbers were intended to denote a very specific die revision, so I have no idea why your SX805 has a different CPUID than the one mentioned on CPUworld. Possibly the entry on CPUworld is wrong?

Disruptor wrote on 2023-03-31, 18:40:

And is there a way to get the contents of what is in the DX register after invoking RESET?

"BIOS stores the CPUID value in CMOS" is not applicable in many standard PCs, although it would be nice. http://www.os2museum.com/wp/intel-486-errata/ implies that IBM PS/2 BIOSes make that value available. While many versions of the Award BIOS do stash the DX value after reset into CMOS location 3B and 3D, that use is only temporary, and gets replaced by an Award-specific CPU code during POST. There are two other known approaches to obtain DX after reset on a PC-like machine:

• Cause a processor reset (triple fault, likely also via KBC) while the A20 gate is disabling A20. This causes the processor to get bad opcodes when it tries to fetch the reset initialization code. If you installed a bad opcode handler, you get the trap, and can read DX. Official documentation states that the processor starts with SS=0, SP=undefined after reset, so entering the invalid opcode handler will overwrite some bytes in the first 64KB. The link to SHUTDOWN.ASM is dead, I couldn't find a mirror quickly, so the example code is currently unavailable.
• Perform a standard reset into BIOS, by use one of the shutdown codes in CMOS register 0F that return to an application program quickly. Those are usually, 04, 05, 09 and/or 0A. Some of them might leave DX untouched. https://mattst88.com/programming/AssemblyProg … ournal/issue/6/ has example code for it (Search for "ID register").

There are tools floating around since the 90s that implement both of these options, too bad I can't remember the name of any of them 🙁 .

mkarcher wrote on 2023-04-03, 15:27:

Are you sure it supports L1WB? As far as I know, "&E" means SMM and CPUID (the "SL enhanced" core), and "&EW" means L1WB support. The picture you link shows "&E".

The SX955 shown in CPUworld is an &EW processor, so that one in fact should support L1WB. I used to think that the S-Spec numbers were intended to denote a very specific die revision, so I have no idea why your SX805 has a different CPUID than the one mentioned on CPUworld. Possibly the entry on CPUworld is wrong?

Thank you for your thoughts and I am not sure in my DX2 supports WB, CHKCPU reports it as supporting WB and it has the same CPUID as the SX955 that does, Jan thinks CHKCPU is correct. I have not found a DEC Venturis 4 BIOS option to enable WB, the SiS 471 chipset supports WB. I keep wondering, could I write to the 471 + CR0 to enable WB?

I also noticed my DX2 supports PSE (Page Size Extension), but my DX4 does not

I posted to CPUWorld asking why my CPU has a different CPUID and as yet the post has not appeared.

red-ray wrote on 2023-04-03, 16:01:

mkarcher wrote on 2023-04-03, 15:27:

Are you sure it supports L1WB? As far as I know, "&E" means SMM and CPUID (the "SL enhanced" core), and "&EW" means L1WB support. The picture you link shows "&E".

Thank you for your thoughts and I am not sure in my DX2 supports WB, CHKCPU reports it as supporting WB and it has the same CPUID as the SX955 that does, Jan thinks CHKCPU is correct. I have not found a DEC Venturis 4 BIOS option to enable WB, the SiS 471 chipset supports WB. I keep wondering, could I write to the 471 + CR0 to enable WB?

Writing to CR0 to enable WB is a Cyrix thing, accompanied by locking the NWT "no write-through" bit to keep the cache in WB. For Intel/AMD processors, the processor enables the WB protocol if the WB/WT pin is pulled high on RESET. If the WB protocol is enabled, the processor samples the WB/WT pin during every cache-line fill, and if the pin is high at that point in time, write-back is enabled for that line. Typically, that pin is jumpered to either "high" or "low" all the time, so in WB mode, all cacheable memory is write-back capable.

It's not just the chipset that needs to support the WB protocol, it's also the routing of the mainboard. Many early mainboards support the classic Cyrix variant of the WB protocol, and optionally also the Pentium Overdrive variant, that uses the extra row of pins. The Intel &EW protocol uses partially the same pins as the classic Cyrix protocol, but in a completely different way. A mainboard that supports write-back on both Intel &EW CPUs and Cyrix CPUs needs to have a set of jumpers (or 0-ohm resister networks) to configure the pinout. Mainboard support for L1WB is a recurring theme on VOGONs, I participated in one of those threads some weeks ago: ABIT AB-AH4 / AB-AH4T Write Back L1 Cache

mkarcher wrote on 2023-04-03, 15:55:

Cause a processor reset (triple fault, likely also via KBC) while the A20 gate is disabling A20.

I can see this being possible when running DOS, but doubt it's possible when Windows NT is running, is it please?

I keep hoping the BIOS will pass the information into Windows NT and the SYSTEM_INFO->wProcessorRevision; returned by GetSystemInfo() will be sensible. It's FFD0 for my Am486 DX2-66 and need to gather information for other CPUs that don't have CPUID.

red-ray wrote on 2023-04-03, 16:24:

I keep hoping the BIOS will pass the information into Windows NT and the SYSTEM_INFO->wProcessorRevision; returned by GetSystemInfo() will be sensible. It's FFD0 for my Am486 DX2-66 and need to gather information for other CPUs that don't have CPUID.

According to https://learn.microsoft.com/en-us/windows/win … api-system_info , FFD0 means: Model 3, Stepping 0. This does not even indicate the presence of a 486 processor at all. I doubt this value will be different on any other non-CPUID 486 you can obtain. Also, I never heard of a mainstream BIOS interface to retrieve the DX-after-reset value.

EDIT: I confused "model" with "family", sorry for that. If Windows NT is able to identify "Model 3", it either guesses "clock doubling" from the CPU clock, or it does indeed get some access to processor detail information. The Award CPU type code, which you can obtain from the CMOS, would allow to tell "DX2" from "DX" and "DX4". Also, Windows NT could perform the Shutdown-with-0Ah method to try to retrieve DX after reset during boot.

I don't think you are able to safely perform the DX-after-reset obtaining methods I described earlier from a running Windows NT system, although it might be possible to pull off the stunt in special circumstances using a kernel driver at ring 0.

BTW: Wheneven I write "Windows NT", that also includes Windows 2000 and Windows XP.

mkarcher wrote on 2023-04-03, 17:01:

red-ray wrote on 2023-04-03, 16:24:

I keep hoping the BIOS will pass the information into Windows NT and the SYSTEM_INFO->wProcessorRevision; returned by GetSystemInfo() will be sensible. It's FFD0 for my Am486 DX2-66 and need to gather information for other CPUs that don't have CPUID.

According to https://learn.microsoft.com/en-us/windows/win … api-system_info , FFD0 means: Model 3, Stepping 0. This does not even indicate the presence of a 486 processor at all. I doubt this value will be different on any other non-CPUID 486 you can obtain. Also, I never heard of a mainstream BIOS interface to retrieve the DX-after-reset value.

Wouldn't model 3 conform with DX=0430h at reset for a 486DX2?

jakethompson1 wrote on 2023-04-03, 17:16:

mkarcher wrote on 2023-04-03, 17:01:

red-ray wrote on 2023-04-03, 16:24:

I keep hoping the BIOS will pass the information into Windows NT and the SYSTEM_INFO->wProcessorRevision; returned by GetSystemInfo() will be sensible. It's FFD0 for my Am486 DX2-66 and need to gather information for other CPUs that don't have CPUID.

According to https://learn.microsoft.com/en-us/windows/win … api-system_info , FFD0 means: Model 3, Stepping 0. This does not even indicate the presence of a 486 processor at all. I doubt this value will be different on any other non-CPUID 486 you can obtain. Also, I never heard of a mainstream BIOS interface to retrieve the DX-after-reset value.

Wouldn't model 3 conform with DX=0430h at reset for a 486DX2?

Thanks for the correction. It does. I edited my original post to add strike through on the invalid statement.

mkarcher wrote on 2023-04-03, 17:01:

I don't think you are able to safely perform the DX-after-reset obtaining methods I described earlier from a running Windows NT system, although it might be possible to pull off the stunt in special circumstances using a kernel driver at ring 0.

Seems like something that Ntdetect or Hal should do and stash somewhere for later?

I wonder how they distinguished a stepping D 486 CPU: https://www.betaarchive.com/wiki/index.php?ti … _Archive/103933 Perhaps just by testing for the bug that affected stepping C and if it isn't buggy, it must be D?

jakethompson1 wrote on 2023-04-03, 17:16:

FFD0 means: Model 3, Stepping 0. This does not even indicate the presence of a 486 processor at all.
Wouldn't model 3 conform with DX=0430h at reset for a 486DX2?

Ah, that makes sense as for it being a 486, that's easy , SYSTEM_INFO->wProcessorLevel is 3 for a 386, 4 for 486, 5 for Pentium and 6 for PentiumPro and later, 31 for Itanium 2.

There is also SYSTEM_INFO->dwProcessorType which can be such as PROCESSOR_INTEL_386, PROCESSOR_INTEL_486 , PROCESSOR_INTEL_PENTIUM, PROCESSOR_INTEL_IA64 , PROCESSOR_AMD_X8664, PROCESSOR_ALPHA_21064, ...

Things change when the CPU has CPUID, my DX2 has Type 486 Level 4 Revision 0306, my DX4 Type 486 Level 4 Revision 0800, my i9-9980XE Type 8664 Level 6 Revision 5504, my Itanium 2 Type 2200 Level 31 Revision 0105, my Alpha 21164A Type 21064 Level 21164 Revision 0002 all of which match what the native CPUID returns.

I just ordered a 486 DX-33 so will see what that reports later in the week. It would be good if we knew what was returned for a new other 486/386 CPUs that do not have CPUID.

So I am happy we can get the model, but suspect AMD vs. Intel will be tricky to impossible.

jakethompson1 wrote on 2023-04-03, 18:08:

I wonder how they distinguished a stepping D 486 CPU: https://www.betaarchive.com/wiki/index.php?ti … _Archive/103933 Perhaps just by testing for the bug that affected stepping C and if it isn't buggy, it must be D?

I'd guess there is no stepping D 486 CPU without CPUID, making the detection quite easy. If you haven't seen it yet, https://retrocomputing.stackexchange.com/ques … -486dx4-machine is also a nice story about CPU detection in NT 3.1

mkarcher wrote on 2023-04-03, 18:45:

I'd guess there is no stepping D 486 CPU without CPUID, making the detection quite easy.

It's the model + stepping that will determine if CPUID is present, and yes, once you have CPUID it all get's way too easy, that said much as the NexGen Nx586-PF110 have CPUID, but the usual CPUID detection code does not work so I changed SIV to just try doing a CPUID within a SEH to deal with CPUID not being supported.

Thank you for the link, I will take a look later.

The next question is what Windows 9X returns as sensible as what Windows NT returns?

mkarcher wrote on 2023-04-03, 17:01:

BTW: Wheneven I write "Windows NT", that also includes Windows 2000 and Windows XP.

For me Windows NT means V3.10 to V10.0, I also feel W11 should be V11.0 😀 Once in a while I try and get SIV to run on NT 3.10, but it really needs 3.51 + newshell2 to work well.

mkarcher wrote on 2023-04-03, 17:01:

https://learn.microsoft.com/en-us/windows/win … api-system_info , FFD0 means: Model 3, Stepping 0.

I just looked at https://www.sandpile.org/x86/cpuid.htm and there are several 486 models > 5 namely as below. I wonder how these are reported. I am pretty are all the Intel ones have CPUID, but am unsure about the others.

1Intel 80486 - still to check	 
2        0 486DX-25/33
3        1 i86DX-50
4        2 486SX
5        3 486DX2 - without CPUID
6        4 486SL
7        5 486SX2
8Intel 80486  - model > 5
9        7 486DX2WB 
10        8 486DX4
11        9 486DX4WB
12AMD 80486
13        7 486DX2WB
14        8 486DX4
15        9 486DX4WB
16        A Elan SC400
17        E 5x86
18        F 5x86WB
19Cyrix 5x86
20        9 5x86

From an Intel Book I have these:

1Intel Microprocessors, Volume I (1992) page 2-17 Table 1-5 and later documentations
2Register             DH      DL           CPUID
3i486 Stepping  Component ID  Revision ID  Instruction
4DX         B3        04      01           no
5DX         B4        04      01           no
6DX         B5        04      01           no
7DX         B6        04      01           no
8DX         C0        04      02           no
9DX         D0        04      04           no
10DX        cA2        04      10           no
11DX        cA3        04      10           no
12DX        cB0        04      11           no
13SX         A0        04      20           no
14DX2        A         04      32           no
15DX2        B         04      33           no
16DX2&OD(WT) ?         04      3x           ?
17SX2OD      ?         04      5x           ?
18DX2&OD(WB) ?         04      7x?          yes?
19DX4OD      ?         04      8x           yes?
20DX4OD      ?         14      8x           yes?
21DX4        ?         04      9x           yes
22PODP       ?         15      3x           yes

In later processors Intel calls x stepping identifier.
Note that Intel mentions that for upgrade processors the value in DH is not 04h but 14h (DX2ODP/ODPR seem to be an exception).
I guess they have nothing to do with the values in NT.
All these CPUs are from a time before the DX2.
DX50 is described in that book. 487SX is marked as preliminary.

According to section 6.5 in that book, the Revision ID is a part in the EDX register after reset:
EDX = 0400 + Revision ID

Boundary scan informations (486 DX 50 PGA 168 Version, 486 SX PQFP 196 Version):

1Component Code  Version Code  Part Number Code  Manufacturer Identify
2i486 CPU (Ax)       00h           0410h             09h
3i486 CPU (Bx)       00h           0411h             09h
4i486SX (cAx)        00h           0427h             09h

I think that boundary scan registers are just available over the JTAG interface.

486 codenames

1P4    - Intel i486DX
2P4S   - Intel i486DX SL Enhanced
3P24   - Intel i486DX2
4P24S  - Intel i486DX2 SL Enhanced
5P24D  - Intel i486DX2 Write Back Enhanced
6P24C  - Intel intelDX4
7???   - Intel intelDX4 Write Back Enhanced
8P23   - Intel i486SX
9P23S  - Intel i486SX SL Enhanced
10???   - Intel i486SX2
11P4T   - Intel i486 Overdrive
12P23T  - Intel i486 Overdrive
13P23N  - Intel i487SX
14P24T  - Intel Pentium OverDrive
15P24CT - Intel Pentium OverDrive

More informations are collected here:
https://ardent-tool.com/CPU/486_Step.html
http://ibmmuseum.com/Interrupts/INT15h/INT15hC9.htm

red-ray wrote on 2023-04-03, 19:53:

I just looked at https://www.sandpile.org/x86/cpuid.htm and there are several 486 models > 5 namely as below. I wonder how these […]
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mkarcher wrote on 2023-04-03, 17:01:

https://learn.microsoft.com/en-us/windows/win … api-system_info , FFD0 means: Model 3, Stepping 0.

I just looked at https://www.sandpile.org/x86/cpuid.htm and there are several 486 models > 5 namely as below. I wonder how these are reported. I am pretty are all the Intel ones have CPUID, but am unsure about the others.

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1Intel 80486 - still to check	 
2        3 486DX2 - without CPUID
3        7 486DX2WB

Wait a second, isn't the SX955 we were just discussing CPUID code 436, so "model 3", and unambigously known as WB capable? So possibly 7 is only used by &EW processors jumpered into WB mode.

red-ray wrote on 2023-04-03, 19:53:

[…]
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1AMD 80486
2        7 486DX2WB
3        8 486DX4
4        9 486DX4WB
5        E 5x86
6        F 5x86WB

Take a look at https://www.amd.com/system/files/TechDocs/20736.pdf : That's for the AMD enhanced 486 processors. "Enhanced" means AMD's own SMM microcode and WB cache support. The variant code on the processor case will be SV8B (for 8K L1 cache) or SV16B (for 16K L1 cache, i.e. the 5x86 processors). That datasheet confirms DX after reset (3/7 for x2, 8/9 for x3, E/F for x4), but is likely wrong at documenting CPUID. I am very confident that CPUID returns the same code as DX-after-reset. You can differentiate a DX4 from a 5x86 using CPUID. This "enhanced DX4" is possibly a not sufficiently edited version of the 5x86 data sheet.

After AMD lost the lawsuit with Intel about IP rights for advanced 486 features, they had to remove the Intel microcode that implements the system management mode. That's when they introduced the "N" letter into their markings. ("NV8T" means "no SMM support; low voltage; 8K L1; write-through). It is likely that the Intel SMM microcode they had to remove also contained the CPUID implementation. I never had a AMD DX2 or AMD DX4 with Intel's microcode, so I can't confirm that. I can confirm that the DX4 NV8T (a common one) does not support CPUID, and a DX4 SV8B (the enhanced one) does support CPUID and returns the codes mentioned in the datasheet as "DX after reset".

red-ray wrote on 2023-04-03, 19:53:

[…]
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1Cyrix 5x86
2        9 5x86

Supports CPUID.