Your theory that the manufacturer added the series diode to reduce heat on the VRM itself is sound. When you look at the board, you see that they had originally intended to screw the VRM down to some ground plane on the motherboard, but no version of this board that I've seen (v0, v2a, v2b, v3, v3.1) has had the VRM screwed down, and yet the VRM never gets warm. They probably realised that the only 4 V CPU available is some oddball Cyrix 486DX, which draws lower currents, and therefore they will probably get close enough to 4 V, like 3.95 V with this CPU. So, save $ on the nut/screw, and instead of doing the regular protection diode, use a heftier diode to serve two purposes. Still, I've never seen this approach taken on a PCI 486 board, but alas, I wasn't looking until now.

On all my MB-8433UUD boards, I have added a trimmer to the 4V option of the jumpers to allow for variable CPU voltages. I am wondering if it would be suitable to merely short this diode, D15, thus allowing for higher voltages to overclocked CPUs? It would be easy enough to add the protection diode noted in the Sharp datasheet, if you think it is necessary. From your commentary, maybe not. Are we trying to protect all other 5V components on the motherboard from reverse current? I'd image the PSU would have this protection already.

When you say you were barely able to get EDO running at 3-1-1-1, 40 MHz, 32 MB - what DRAM wait states were the fastest functional? If 0ws/0ws, then all hope isn't lost. At 66 MHz, if we can use 3-1-1-1 and 1ws/0ws, this might be acceptable.

What is your source for CY7C1009BN? I don't see this P/N on mouser or digikey. Looking forward to you [eventual] SRAM gadget.

feipoa wrote on 2023-03-16, 10:13:

On all my MB-8433UUD boards, I have added a trimmer to the 4V option of the jumpers to allow for variable CPU voltages. I am wondering if it would be suitable to merely short this diode, D15, thus allowing for higher voltages to overclocked CPUs? It would be easy enough to add the protection diode noted in the Sharp datasheet, if you think it is necessary. From your commentary, maybe not. Are we trying to protect all other 5V components on the motherboard from reverse current? I'd image the PSU would have this protection already.

The diode in the data sheet is meant to protect the sharp regulator chip itself. Many of those linear voltage regulators have a really good safe operation area limitation that limits output current and regulator temperature so they are nearly unbreakable (at least unless they start oscillating). But this safe operation area limitation only works if the input voltage is higher than the output voltage. The diode is meant for the case that you have like 1000µF output capacitance, charged to maybe 10V, and suddenly short the input. In that case, the charge of the output capacitors flows through the PQ30RV21 chip, and there is no component in the path to limit the current. The PQ31RV21 will likely overheat and fail short circuit if that much energy is dissipated in it in a very short time. That means, when you apply (lets imagine) 15V input power again, it will pass those 15V unregulated, which will likely kill the 10V side. The diode mentioned in the datasheet will have a lower forward voltage than the uncontrolled parasitic current channel inside the PQ30RV21, so in case of a sudden short circuit on the input side, most of the energy is dissipated in the parallel diode. Beefy silicon rectifier diodes are excellent at handling short current spikes without blowing or melting to a short circuit, so that will protect the regulator chip.

On the Biostar board, it looks like the output capacitance is less than 200µF, and it will be charged to 4V at max, so I doubt there is enough energy on the output side of the chip to burn it.

feipoa wrote on 2023-03-16, 10:13:

When you say you were barely able to get EDO running at 3-1-1-1, 40 MHz, 32 MB - what DRAM wait states were the fastest functional? If 0ws/0ws, then all hope isn't lost. At 66 MHz, if we can use 3-1-1-1 and 1ws/0ws, this might be acceptable.

It was 0/0WS, as listed in the table in the initial post. I assume in EDO mode, wait states are only added to the leadoff cycle, so you could go to 4-1-1-1 or 5-1-1-1, but the actual limitation is the 1-cycle burst which you can't counter by adding waitstates, only by switching to the 2-cycle burst. And in that case, FPM mode seems to beat 2-cycle EDO mode.

feipoa wrote on 2023-03-16, 10:13:

What is your source for CY7C1009BN? I don't see this P/N on mouser or digikey. Looking forward to you [eventual] SRAM gadget.

When I checked for availability yesterday, I found them at Digikey as 2156-CY7C1009BN-12VC-ND, but I didn't notice that it is a marketplace product (I don't know the reputation of Digikey marketplace sellers), and especially I didn't notice that I would have to buy 228 of them. I got mine from a less reputable source (I don't remember, I bought them some years ago with the intention to adapt them from SO32 to DIP32 but never did so. The source might be Aliexpress).

Thank you for the description. Where did you optain that 200 uF value? I haven't noticed many 486 motherboard manufacturers or VRM interposer manufacturers using these external protection diodes on Vout/Vin. Perhaps it is included on the VRM itself on some models.

What are your plans for your 8433UUD board?

I didn't know there was a Digikey Marketplace. It would be nice to have a company like Digikey serving as a intermediary for the numerous IC warehouses which contain NOS and hard to find parts.

feipoa wrote on 2023-03-17, 10:54:

Thank you for the description. Where did you optain that 200 uF value?

I guessed from what I saw near the processor socket. There are four capacitors in a case size that is typical for caps of 22µF or 47µF, so I guessed 200µF for four of them (assuming they are all on Vcore, not on +5V) to be on the high side. I admit that I didn't check that, though.

feipoa wrote on 2023-03-17, 10:54:

I haven't noticed many 486 motherboard manufacturers or VRM interposer manufacturers using these external protection diodes on Vout/Vin. Perhaps it is included on the VRM itself on some models.

The same as for the 8433UUD also applies to these interposers, possibly even more: There is not a lot of capacitance on the Vcore side, so there is not enough energy to kill the regulator if the input gets shorted, so this diode isn't strictly required. Too bad the data sheet doesn't include an "abs max" value for reverse voltage or current.

feipoa wrote on 2023-03-17, 10:54:

What are your plans for your 8433UUD board?

I'm not yet fully decided. I will do the Schottky mod, the 5k trimmer mod, and intend to make that 1MB cache PCB. The processor should be some kind of 5x86, either the 100GP that seems to work at 120MHz with BTB_EN (at least with a fan and in winter times), or a S16VB (yeah, that's the other 5x86) at 160. Maybe I try 180 again, possibly at 3.8V. I tried it on a Soyo 4SA board, and 3*60 worked well enough for a single benchmark, then it stopped working. I have no idea whether that "worked only once" is a sign of being lucky, or whether running 180MHz / FSB 60 caused permanent component degradation. I need to re-fix some battery damage on that board, though, so currently no plans for the 4SA yet.

feipoa wrote on 2023-03-16, 10:13:

What is your source for CY7C1009BN? I don't see this P/N on mouser or digikey. Looking forward to you (eventual) SRAM gadget.

That chip has been superseeded by the CY7C1009D. I see it offered for ~3,60€ / piece (at qty 10-100) on Mouser (in stock!) at the 10ns speed grade. While that price is not extremely cheap, the chance of getting genuine 10ns SRAM on a 486 board sounds stunning. Also there are news from the gadget front. The PCB has been ordered today! If it works, or if I lose interest in that project, I will publish the design as open-source HW. Some sneak peek for you:

Those are 3D renderings by KiCad. It doesn't include a model for narrow SOJ-32 chips, so the pads are empty in those pics. Also, please don't plug those big square pin headers shown on the image into IC sockets. That will damage the sockets! Use proper IC headers instead - again, I didn't find IC headers in the KiCad library, that's why it's rendered with the square pins. And don't expect the final product to be solderless. 😀

Yup, not cheap. $53.31 CAD for 10 pieces, plus tax and shipping, $80 CAD delivered. Can save $20 in shipping if spending $100 CAD or more.

How does this PCB connect to the MB-8433UUD?

feipoa wrote on 2023-04-03, 23:09:

How does this PCB connect to the MB-8433UUD?

The pins on the "back side" should be IC header pins (round, thinner than displayed) and they plug directly into the cache sockets of the board. All signals and power is taken from the cache sockets, except for A19, which just isn't there.

Wouldn't you want to use all the motherboard's female cache sockets to connect to the male pins on the PCB, even if unused, for increasing hold-on strength?

feipoa wrote on 2023-04-03, 23:32:

Wouldn't you want to use all the motherboard's female cache sockets to connect to the male pins on the PCB, even if unused, for increasing hold-on strength?

It connects into all sockets, but not into all pins.The pins to connect to the sockets are through-hole. The SOJ chips don't fit mechanically between the connection pins, so I have to leave out a lot of pins to be able to place the cache chips. The current design connects has little more than the required pins per bank, but it adds some pins in the corners for mechanical stability. Looking at the picture, I found that one of the ground pins is offset by 2.54mm, but I can just omit that one badly positioned pin, and still get enough holding strength. The ground pins are connected to a ground plane, so a missing ground pin will not invalidate the design. I already fixed the PCB layout on my working copy.

I used the phrase "female cache sockets" to refer to the individual holes on the cache socket; I could not think of a better word to address the individuality. On the male end, one would just say "pin" to refer to the individual pins, but on the female end, I guess I could have used the term "individual holes".

I will be interested to see if this works well. In looking at your board, I don't see the 10K resistor to be used on TAG A15 and A16.

Do you you also have a VCC plane? How many layers is the PCB?

feipoa wrote on 2023-04-03, 23:58:

I will be interested to see if this works well. In looking at your board, I don't see the 10K resistor to be used on TAG A15 and A16.

Why would you need resistors on the TAG address bits? This board is not meant to be adaptable to different cache sizes, it only works with 9 chips of 128k x 8. So there is no need to interrupt address lines and fall back to pull-up resistors. Actually, that board uses the data address bits from bank 2 for the tag, too. This simplifies routing a lot.

feipoa wrote on 2023-04-03, 23:58:

Do you you also have a VCC plane? How many layers is the PCB?

Two layers, no VCC plane. That's why there is a reservoir/filter cap next to each cache chip. One pad of each cap is connected to the ground plane, and the other one is close to the VCC pin of the individual cache chip. The low impedance of the cap (at high frequency) will provide a low-impedance VCC even without a VCC plane, just because we have a low-impedance ground plane.

It has been about 8 years since I have looked into this modification. In preparation for this modification, I looked at the convention used on 3 or 4 other motherboards for 1024K. In my MB-8433UUD manual, page 8, which describes the details for this cache mode, I have noted:

4) Solder in a 10K SMD resistor between TAG A16 and Vcc on TAG DIP-32 extension
5) Solder in a 10K SMD resistor between TAG A15 and Vcc on TAG DIP-32 extension

I do not recall my reasoning for this, and perhaps this step is not necessary, but I likely added these resistors to follow the convention used on other boards.

Concerning the caps, do you recall if the sockets on this motherboard also have filtering caps for each DIP? if not, perhaps I should add some to my DIP extension. EDIT: Looks like yes they do, at least in quick view under the sockets from this image, download/file.php?id=159894&mode=view

feipoa wrote on 2023-04-04, 00:47:

It has been about 8 years since I have looked into this modification. In preparation for this modification, I looked at the con […]
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It has been about 8 years since I have looked into this modification. In preparation for this modification, I looked at the convention used on 3 or 4 other motherboards for 1024K. In my MB-8433UUD manual, page 8, which describes the details for this cache mode, I have noted:

4) Solder in a 10K SMD resistor between TAG A16 and Vcc on TAG DIP-32 extension
5) Solder in a 10K SMD resistor between TAG A15 and Vcc on TAG DIP-32 extension

I do not recall my reasoning for this, and perhaps this step is not necessary, but I likely added these resistors to follow the convention used on other boards.

You need these resistors to prevent open inputs for lines that are optionally driven by the processor address. This happens if there is a jumper that can interrupt address lines for smaller cache sizes. In case of your mod, the resistor on TAG A16 is on a line that is never driven by the processor. A resistor also works fine in that case, but you could as well tie the line to ground or Vcc with a trace, and that's what my adapter PCB does. TAG A15 is always driven by the processor, because there is no jumper interrupting the connection between FSB A19 and TAG A15. This should also imply that you can not properly downgrade to 512K or 256K of cache, because in that case, A19 would need to be interrupted.

My cache module PCB allows CPU A19 to be interrupted: Just unplug the pin labelled "CPU A19" that is intended to be be connected to A19 of the frontside bus using a DuPont-style wire. In case you do, the behaviour of my module will get erratic, as there is nothing but that pin driving the address lines of the cache chips. With my module, you would be responsible to connect that pin to Vcc or GND externally if you don't want 1MB of cache. I can easily bodge in a resistor to Vcc on my PCB, the published open-source version will likely have that resistor added, so you can also use the module in 512K dual-bank mode without external connection of the A19 pin.

feipoa wrote on 2023-04-04, 00:47:

Concerning the caps, do you recall if the sockets on this motherboard also have filtering caps for each DIP? if not, perhaps I should add some to my DIP extension. EDIT: Looks like yes they do, at least in quick view under the sockets from this image, download/file.php?id=159894&mode=view

Agreed, it looks like there are SMD caps below the sockets. That's the optimal position for DIP32 chips. I added the extra caps to the adapter PCB, because the important metric is trace length from the capacitor to the cache chips. The interposed module and especially the orientation of the second bank (it's rotated by 180 degrees for layout reasons) add extra trace length, so adding another set of capacitors is playing safe. The caps are cheap and there is no issue with PCB space, so I decided to stop worrying and added the caps.

Yes, I think it would be good if your PCB can be easily adapted to 512K, assuming these 10 ns SOJ chips are still available.

mkarcher wrote on 2023-04-04, 07:16:

You need these resistors to prevent open inputs for lines that are optionally driven by the processor address. This happens if there is a jumper that can interrupt address lines for smaller cache sizes. In case of your mod, the resistor on TAG A16 is on a line that is never driven by the processor. A resistor also works fine in that case, but you could as well tie the line to ground or Vcc with a trace, and that's what my adapter PCB does. TAG A15 is always driven by the processor, because there is no jumper interrupting the connection between FSB A19 and TAG A15. This should also imply that you can not properly downgrade to 512K or 256K of cache, because in that case, A19 would need to be interrupted.

The instructions I noted in my Biostar manual were strictly for the 1024K mod. I have not yet, and possibly never will, update the manual to include the jumper-able configurations for 512K/1024K double-banked, even though I have been using the motherboard in the jumper-able configuration for many years. Concerning A15, this is was the new jumper block to switch between 512K and 1024K:

My notes say to remove the two jumpers for 512K double-banked.

feipoa wrote on 2023-04-04, 08:39:

Yes, I think it would be good if your PCB can be easily adapted to 512K, assuming these 10 ns SOJ chips are still available.

I already included the resistor on CPU A19 / Cache A16 / Tag A15 into the design that will become "v1.0". And as I said, it's easily bodged on in the prototype design, and even without that resistor, the prototype is fully usable at dual-bank 512K when you just connect A19 to Vcc or GND. The current routing on the adapter does not support single-bank operation. Unless there is strong demand, I do not intend to implement single-bank operation. Are you suggesting 512K as 4* 128k x 8, as already supported with DIP chips, or 512K as 8* 64k x 8 (dual banked, not implemented on the Biostar board)? If you intend single-bank 512k to save on chip costs, I need to put some thought into clever routing, as I currently "optimized away" the single-bank support.

feipoa wrote on 2023-04-04, 08:39:

The instructions I noted in my Biostar manual were strictly for the 1024K mod. I have not yet, and possibly never will, update the manual to include the jumper-able configurations for 512K/1024K double-banked, even though I have been using the motherboard in the jumper-able configuration for many years. Concerning A15, this is was the new jumper block to switch between 512K and 1024K:
v3_manual_new_jumper_block.JPG

My notes say to remove the two jumpers for 512K double-banked.

That sounds completely correct. Likely one of the jumpers will interrupt A19 going to the data RAM, and the other one will interrupt A19 going to the tag RAM. With the jumpers removed, a resistor to Vcc is required to keep valid operation. The non-jumpered configuration from your manual doesn't require the resistors. You just got them from copying mainboards which supported jumpering.

My statement was only to serve as an agreement - ensure the PCB can be used for 1024K double-banked and 512K double-banked, which it seems like you are planning for.

Small word of caution: SRAM module binning may be required to get 1024K working at 2-1-1-1 w/33 MHz and cx5x86. I think user pshipkov experimented with this and found this board to be very SRAM particular. For the quick tests I did with 1024K and 33 MHz, I couldn't get 2-1-1-1 working w/cx5x86. I didn't spend much time on this because I was targeting 1024K for 66 MHz FSB and 3-2-2-2. I noticed that this board lacks buffers, could this by why 2-1-1-1 was not working well with 1024K? On my other boards, which have the memory buffers, 1024K and 2-1-1-1 was never an issue at 33 MHz.

EDIT: Would there be space for SOJ sockets to swap the SRAM on your PCB?

feipoa wrote on 2023-04-04, 11:20:

My statement was only to serve as an agreement - ensure the PCB can be used for 1024K double-banked and 512K double-banked, which it seems like you are planning for.

Yes, 512K with A19 grounded, pulled to 5V (directly or using a 10K resistor) makes an plug-and-play experience to get to 512K without any hardware support. With the builtin resistor, it's actually unplug-and-play 😉 .

feipoa wrote on 2023-04-04, 11:20:

Small word of caution: SRAM module binning may be required to get 1024K working at 2-1-1-1 w/33 MHz and cx5x86. I think user pshipkov experimented with this and found this board to be very SRAM particular. For the quick tests I did with 1024K and 33 MHz, I couldn't get 2-1-1-1 working w/cx5x86.

Now, that's funny. I had no issues with 2-1-1-1 at 40MHz on the Biostar board and RAM WS 0/0 with the 5x86. I did need 1/0 on RAM WS to get stable operation on the HOT-433 with an earlier 8881 revision, though.

This experience is at 256KB cache, but as long as the capacitive load of the chips is approximately the same for 128K x 8 chips, as it is for 32K x 8 chips, stability and timing shouldn't depend on the cache size. On the other hand, there are these notorious IS61C1024N-10 DIP32 chips from China that are definitely fake (in the sense that they were not manufactured by ISSI and specified for 10ns access time), and possibly just way slower than the 32k x 8 chips we typically use for 256K of cache. Nevertheless, the requirement to add a read wait state on the HOT board at FSB40 for the Cyrix, although an AMD 5x86 works perfectly at FSB40 with 0 read wait states confirms that the Cyrix 5x86 is more picky about memory timing than the AMD 5x86.

I didn't spend much time on this because I was targeting 1024K for 66 MHz FSB and 3-2-2-2. I noticed that this board lacks buffers, could this by why 2-1-1-1 was not working well with 1024K? On my other boards, which have the memory buffers, 1024K and 2-1-1-1 was never an issue at 33 MHz.

Indeed, buffers on the memory data lines might help, as they reduce capacitive load on the frontside bus. On the other hand, buffers on the memory data lines also increase memory access time by 3 to 8 ns, depending on the buffer type. Buffers on the memory address lines on the other hand (which are more common than on the memory data lines) are likely unrelated to cache timing, because the row/column-multiplexed memory address lines are completely separate from the frontside bus address lines. Address buffers are more common, because every memory chip connects to every address line, whereas only every memory rank connect once to each data line, so strong drive is way more important on the address lines than on the data lines.

EDIT: Would there be space for SOJ sockets to swap the RAM on your PCB?

No. I'm already using the narrow SOJ variant. It has a 0.3 inch wide body, just as the "skinny DIP" 28-pin and 32-pin cache chips. The distance between neighbouring DIP sockets on the Biostar board is 0.4 inch (which is common), so there is only 0.05 inch space between the edge of the chip case and the border of the socket. This is sufficient for DIP sockets, but as SOJ sockets can only clamp from the outer edge, they are wider. The current layout is created with the fact in mind that the SOJ chips are placed at the same period as the DIP sockets. This will make soldering them an interesting challenge, and is the reason why I ordered a SMD hot-air station and soldering paste in a syringe. I guess I wouldn't be able to solder that board with my home improvement heat gun (it will just blow away the chips), and using an iron might also prove challenging.

The CY7C1009D has the "classic" pin layout the DIL chips had, but these chips are increasingly hard to find. If you can manage to adopt your PCB-layout to the later pinout (with Vcc pins at the center) sourcing the chips would be far easier in the future.

majestyk wrote on 2023-04-04, 15:05:

The CY7C1009D has the "classic" pin layout the DIL chips had, but these chips are increasingly hard to find. If you can manage to adopt your PCB-layout to the later pinout (with Vcc pins at the center) sourcing the chips would be far easier in the future.

Are you talking about the CY7C1049G for example, a 512K x 8 chip? Or the CY7C109D-10Z in TSOP32? With mouser having around 3000 CY7C1009D-10V (narrow SOJ) in stock right now, I wouldn't call them "hard to find", but the 109D-10Z is considerably cheaper. Post a datasheet link of the chip you suggest to use, and I might see if I can do another variation. I'm definitely running finishing the SOJ32 project first, though. Let's see whether the chips I ordered some years ago and never got around to use are any good. They are some kind of CY7C1009, although I can't remember the source, and I currently don't have them at hand to check whether they are the older "B" variant or the newer "G" variant. It's possible I got them from a chinese reseller, and as I didn't do any thorough inspection, they might turn out to be relabelled slower chips. If they perform bad, chances are high I give the project a second try with a different pinout.

mkarcher wrote on 2023-04-04, 11:55:

Now, that's funny. I had no issues with 2-1-1-1 at 40MHz on the Biostar board and RAM WS 0/0 with the 5x86. I did need 1/0 on RAM WS to get stable operation on the HOT-433 with an earlier 8881 revision, though.

This is correct, 2-1-1-1-1, 0ws/0ws, 40 MHz, cx5x86, and 256K is not an issue, even with the fake chinese 32kx8 chips. The issues start after 256K. This was the primary reason I decided to include a 512K double-banked option on my Biostar board. I recall all brands of motherboards I tested to have issues with 1024K, cx5x86, 3x40 MHz, 2-1-1-1, 0ws/0ws. Usually the Am5x86 can pass this condition (normally when there are buffers), but not the Cyrix. Total memory installed also comes into play. I had started a massive Excel sheet tracking this phenomenon at various FSB, wait states, RAM totals, CPU, motherboard, etc. but it became too frustrating to work on and I quit after about 100 data points. I can send you the Excel sheet if you wish, but I don't think it will be of much help.

Are there any socketable 10 ns SRAM chips you can use on a revised PCB version? I know there is one other user here who was hoping to see this PCB socketed. Once you get to the extreme fringe of stability with overclocking (be it CPU freq or wait states), dozens of [brand name] SRAM modules needed to be swapped around to achieve stability. User pshipkov knows more on this front.