First post, by megatog615
- Rank
- Newbie
I have this 486 board by PCPartner(part of a VTech Laser 486SX/3). It has four 32-pin cache sockets and two 28-pin TAG/dirty sockets(I am speculating here). I lost the documentation for this machine years ago(and lament it every day), but I have tried various configurations of cache.
Unfortunately I am having trouble getting it working; sometimes when I install cache chips it will hang when loading DOS(specifically, when it tries to load HIMEM). Other times I get corruption on the screen. No matter what configuration I try, the BIOS always shows "256K Cache Enabled"(if it POSTs without error) even though the chips I install aren't always 256K. Other times the POST screen will complain that the cache memory is bad and that I shouldn't enable cache. I installed a set of rare 32-pin sram chips and one of them let out magic smoke and could cook an egg with how hot it got!
I have figured out a few things that may be possible:
- The cache messages are fake(which I think is unlikely).
- My cache chips are bad or fake.
- The board has no jumpers for cache besides enabling parity and the chipset is auto-detecting cache presence.
- The board seems hard-wired for a 256K jumper setting possibly, given how other PCPartner boards of the same era were laid out.
- I genuinely cannot math out the correct chips to order because of how confusing the actual amount of memory they are advertised to handle(256K = 32Kx8??? Okay, so do I need 512K chips rated at 64Kx8 to fill 4 sockets for 256K? What about TAG? Are both the sockets TAG? Or is it a TAG and a dirty socket? What math do I have to do to figure out what to put in those?)
- I have been told that some chipsets actually can't handle cache and will hang when it is installed. This seems to track in my case and I'm beginning to lean on this possibility.
I think I'm at my wits end with this thing. It really sucks how a 486DX @50MHz seems to be really hampered by a lack of L2 cache. Perhaps the wizards on this board can help me. Specifically, I am wondering what other people have done to get cache working in this exact configuration(256K, 4 sockets, 2 TAG/dirty sockets rather than the more common 8 sockets, 1 TAG).