First post, by mkarcher
I recently ran experiments on my MB-8433UUD-A at FSB50. That board has the latest revision of the north bridge, including EDO RAM support (usefulness is quite debatable, but that's no topic for this thread) and the 1:2/3 PCI divider. This divider seems to be perfectly made for FSB50, resulting in PCI33. Yet, I get strange issues with missing characters on the graphics card and I got a crash running a program off a network drive, so likely corrupted network data, too. These issues were perfectly fixed by changing the PCI divider to 1:2, and they also don't appear at 33MHz with the PCI divider at 1:1.
So, time to take out my scope and look at the PCI clock signal. The signal has been scoped on a card, after a 33 ohm series termination resistor. This might slightly increase the rise time/fall time. Likely, that's not the primary limitation in the signal fidelity on my scope pictures. They were taken with a cheap 60MHz 1:10 probe and a flying ground leap clamped to the case near the card I was probing the clock on. So, don't try to judge signal quality, including undershoot/overshoot from these picture. That's not the point of the measurement and the signal detail fidelity might be unsufficient make definite conclusions.
Let's first look at the 33MHz PCI clock signal generated at FSB33 and a 1:1 divider:
The box in the lower right edge of the scope screen displays the time between the two "cursors" (the dashed vertical lines). It is 30ns. If the lines delimit a whole cycle of a periodic wafeform, this would represent a frequency of 33MHz. The PCI clock is meant to be symmetric (it should be "high" as long as it is "low"). The specification calls for a 11ns period in which the signal is "clearly high" and a 11ns period in which the signal is "clearly low". The transition time (rise time / fall time) is allowed to be up to 4nsEDIT: up to 1.2ns from 0.8V to 2.0V for both getting high and getting low. This signal is clearly in specification. Let's look at the "low" time:
If the signal is symmetric, the lower half and the upper half of the waveform should take 15ns each. I tried to measure the "low half", and got 14.8ns, which is close enough to 15ns, to be true, considering me eyeballing what "the low half" is, and the general precision of my measurement setup, this is spot-on. As I already mentioned in the introduction, my measurement setup is definitely increasing rise/fall times, so even if you get 9ns or 10ns "really low" (below 0.8V, as the specification for 5V PCI requires) from that scope picture, there is no reason to believe that the requirement of getting 11ns is violated.
Now, let's look at the PCI clock at FSB50 and a divider of 1:2/3:
This signal looks anything but symmetric! The most likely reason how this happens to happen: The board is running at a 50MHz clock. This means a whole clock period takes 20ns. So the input clock signal is 10ns low and 10ns high. There is an edge every 10ns. There is no edge 15ns after another edge! So the easiest way to divide by 2/3 is to keep the PCI clock low for two edges (20ns) and keep it high for one edge (10ns). As long as your hardware only care about the time between two rising edges of the PCI clock (the clock period), this is fine. The clock period displayed in the bottom right box is 29.8ns, which is close enough to 30ns. On the other hand, the requirement of the clock being "clearly high" for at least 11ns is obviously violated.
As the signal I measure is a reaction to the chipset trying to pull it low or high, it is valid to assume that the chipset starts outputting "high" around the time where the signal suddenly starts to rise, and starts outputting "low" around the time where the signal starts falling after being high for a short time. Let's measure the duration of suspected "high" output:
And indeed: 9.5ns. Maybe the actual time point where the chipset started outputting low is a bit later than the "E"(nd) cursor in that screenshot. The decreasing voltage at that instantant might just be ringing of the high level. Yet, this is close enough to 10ns to validate my hypothesis of a 10ns high output. Obviously, the suspected low part is around 20ns:
So, what does this mean in practice: My non-representative study shows that a Trio64/V+ graphics card, a ARK2000PV graphics card and an RTL8029 network cards all operate unreliable with this shape of PCI clock. This is all the cards I have tested, so the result is a failure rate of 100%. If you get issues at FSB50 with the seemingly correct PCI divider 1:2/3, just switch down to 1:2. This post explains the technical reason for it.
EDIT: Fixed a bad quote from the PCI specification: The rise/fall time is not allowed to be 4ns, but the rate must be between 1V/ns and 4V/ns, so the maximum rise time for "clearly low" (below 0.8V) and "clearly high" (above 2.0V) is 1.2V / (1V/ns) = 1.2ns. The minimum permitted rise time is 0.3ns. That's what I get for not reading the specifications with enough attention to detail...
