Version 1.1 was recently merged, no actual test changes but the test disassembly was updated.

I've been playing around with data mining the tests with Python. Here's an example of the sort of thing you can do, histograms of cycle execution time for all 8088 instructions:

warning: big image

I have uploaded a new version of the 8088 tests, V2.

• 50% of included instructions now run from a full prefetch queue. This vastly improves visibility of actual cycle timings for short instructions that would otherwise be bus-limited. I even found a few off-by-one cycle errors in MartyPC.
• The value of the 20-bit multiplexed bus is now included per-cycle, instead of presenting the "address latch". Various status flags are encoded on the bus pins during various t-states, so the information may be useful if you are developing pin-accurate emulation.
• Fixed a bug in the V1 test generator that did not preserve the value of undefined flags from the CPU. I regret this error made V1 useless for researching or validating undefined flags. V2 should now be a valuable resource for researching undefined flag operation.
• Switched CPUs from the Harris 80C88 to an AMD D8088 1982. There are tiny variances in behavior of the Harris 80C88 used previously. Unlikely to be of any particular concern to most.