Reply 20 of 30, by reenigne
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reenigne wrote on 2023-09-07, 12:30:I'm not actually sure if the CGA loads the character or attribute first, now you mention it. I had been assuming character, but it's not actually very easy to tell from the schematic (and not observable from software either - at least not easily).
I've now determined that it's not observable from software, and have made myself a diagram showing when everything happens within each 16-hdot CGA cycle. Because of the pipelining induced by the various latches, it actually takes about 32 hdots from when the CRTC outputs a new address until the last pixel of the corresponding character hits the monitor cable.
Counting in hdots:
0: CRTC starts outputting address for location 0.
6: CRT address latched for location 0.
6.5: CRT RAS (Row Address Strobe) output enabled for location 0.
8: RAS for location 0. CRTC starts outputting address for location 1 (+HRES only).
8.5: CRT CAS (Column Address Strobe) output enabled for character 0.
9: CAS for character 0.
11: Character 0 data latched.
12: CRT CAS changed to odd address for attribute 0.
12.5: CAS for attribute 0.
14: CPU or CRT(+HRES) address latched for location 1.
14.5: CPU or CRT(+HRES) RAS output enabled for location 1.
15: attribute data latched (+GRPH only).
16: Row Address Strobe for location 1. Attribute data latched (-GRPH only). Shift register loaded and starts outputting hdot 0.
16.5: CPU or CRT(+HRES) CAS output enabled for character 1. Output buffer starts outputting hdot 0.
17: CAS for character 1. Shift register starts outputting hdot 1.
17.5: Output buffer starts outputting hdot 1.
18: Shift register starts outputting hdot 2.
18.5: Output buffer starts outputting hdot 2.
19: Character 1 data latched. Shift register starts outputting hdot 3.
19.5: Output buffer starts outputting hdot 3.
20: CRT(+HRES) CAS changed to odd address for attribute 1. Shift register starts outputting hdot 4.
20.5: CAS for attribute 1. Output buffer starts outputting hdot 4.
21: Shift register starts outputting hdot 5.
21.5: Output buffer starts outputting hdot 5.
22: Shift register starts outputting hdot 6.
22.5: Output buffer starts outputting hdot 6.
23: Shift register starts outputting hdot 7.
23.5: Output buffer starts outputting hdot 7.
24: Attribute 1 data latched (+HRES-GRPH only). Shift register loaded and starts outputting hdot 8.
24.5: Output buffer starts outputting hdot 8.
25: Shift register starts outputting hdot 9.
25.5: Output buffer starts outputting hdot 9.
(and so on for hdots 10-15).
This sequence overlaps (offset by 16 hdots) the next cycle over.
It's unfortunate that attribute (odd) byte 1 is not latched in +HRES+GRPH mode, or more interesting things could be done with this improper mode. But that would have required more gates and the CGA doesn't have enough VRAM for a 640x200x4 image.