VOGONS


First post, by GloriousCow

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In my course of investigating my bus capture of Area 5150's "Lake" end credits effect, I discovered something interesting.

The effect goes through a chain of interrupts that set up a vsync interrupt that triggers each frame of the effect. The purpose of the chain is to position the interrupt at a specific point on screen that isn't strictly at display enable or some other easily pollable location. I've noticed that despite my best efforts I seem to have a bit of inaccuracy with where MartyPC comes out of the interrupt chain vs where hardware does.

The bus sniffer shows something quite interesting:

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half vsync analyzer
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On the Motorola 6845 CRTC a vsync is always 16 scanlines tall. That's sort of taken for gospel; the Amstrad CPC compendium just states it several times. And yet, here we have an 8 scanline vsync.
This is taken right off the CRTC's VS pin, so we're not dealing with any of IBM's shenanigans.

Moreover, there's no indication on the CRTC that a vsync should be appearing here. Looks like a case of phantom vsync.
VileR put together a nice article on the subject here: https://int10h.org/blog/2023/03/cga-6845-crtc … m-vsync-glitch/

there's just one problem - vsyncs, phantom or not, are always 16 scanlines, tall, aren't they?

I went back to VileR's capture of Area 5150 on youtube, and by some miracle, wouldnt you know, at 8:26 ...

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half vsync screenshot
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there she be. this 'impossible vsync' is, unfortunately included in Area 5150's effect interrupt setup timings. Talk about breaking your emulators...

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 1 of 9, by VileR

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Thanks for the heads-up about this (and a big hats-off for the whole bus-sniffing and visualization setup)!

Here's my hunch about what's going on: the answer probably lies in how the 6845 counts those 16 scanlines. A vsync pulse always seems to start and end 8 hdots before a new scanline begins, which you can see from the screenshot above as well. Most likely, the CRTC simply keeps VS high until HTotal has been reached 16 times, i.e. C0=R0 (see footnote #1 in the "phantom vsync" article). Part of the trickery in this effect is that HTotal is in fact reached twice per *physical* scanline - as far as the CRTC is concerned, 16 scanlines have elapsed, but only 8 for the monitor, so that actually checks out.

(I've also replied as much in the blog comments, but there's no notification on those, so putting this here as well.)

BTW, this one might actually be a "true" vsync rather than a "phantom" one; it just takes a couple of frames for vertical sync to settle at the beginning of the effect, so it's inadvertently visible, but it's placement with respect to the top of the image looks about right.

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Reply 2 of 9, by GloriousCow

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I'm suspicious that it's a phantom vsync for a few reasons - mostly because MartyPC doesn't see any reason to do a vsync at all at that point, and the alternative is I just have a gross misunderstanding of the CRTC somewhere, which is a reality I wish to reject for the moment.

This is immediately after the first invocation of the effect ISR. When the effect ISR triggers, R4 is 63 and R7 is 25. The effect ISR sets R4=1 at the marker i have indicated below. That means vsync should be suppressed until the demo decides to allow it to happen again by setting R4 > R7.

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more sniffing stuff
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the last thing that happens before the vsync is setting R2 to 57h:

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yet more sniffing stuff
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i can't see how that's related though. IP at the point of vsync is 5C9 is just right in the middle of the normal effect routine; nothing vsync-related should be happening ?

EDIT: I suppose that's irrelevant, any trigger would need to be at least a character clock before...

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 3 of 9, by VileR

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The screenshot seems to at least strongly suggest a non-'phantom' vsync, since the beginning and the end of the blanking period are neatly lined up vertically; both seem to occur at the last character of the scanline period, which is what you see with a normally-scheduled vsync. A phantom vsync would start blanking as soon as the triggering write occurs, so in this case, it'd have to be timed to that specific instant.

Anyway, if R7 has remained the same since before the ISR invocation, and wasn't rewritten just before VS went high, then I don't think it can be a phantom - R2 should be unrelated to the VS-related checks, and the only cause I've been able to identify for phantoms are modifications to R7.

How are the 6845 scanlines being counted alongside the sniffer data, and/or in MartyPC? If the "two 6845 scanlines per monitor scanline" trick isn't properly taken into account, I suppose the emulated CRTC may be miscounting scanlines starting from the point when that trick is initialized... perhaps that's why MartyPC does not fulfill the condition for a vsync at the point where the hardware does?

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Reply 4 of 9, by GloriousCow

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Sorry, yes, you're right. I was just proving that to myself by decoding the video 'stream' from the bus traces and then drawing all writes to 3D4 on top of it.

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Lake effect CRTC timings
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The bus decoder has no concept of CRTC register state (yet) so it just ticks a scanline every hsync. that's fine, because that's MartyPC's conception of a scanline, too.

Once the effect starts doing its thing with the two side by side rows I need to start counting each of those toward R7.

I was thrown off by thinking that R4 was 1, but at the time it is set, we are overflowing it, so it isn't really relevant.

Well, that's a relief because it's literally a one line fix. I did NOT want to try to emulate phantom vsyncs. Thanks for your help.

EDIT: Are any of you guys working on a blog post about the Lake effect? Because it's screaming for one, and I think I am well positioned to write one with some cool visualizations, but if we are going to hear it from the horse's mouth so to speak, I will not try to steal y'alls thunder...

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 5 of 9, by VileR

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GloriousCow wrote on 2023-10-14, 23:15:

Well, that's a relief because it's literally a one line fix.

My favorite sort of fix. 😀 Nice!

EDIT: Are any of you guys working on a blog post about the Lake effect? Because it's screaming for one, and I think I am well positioned to write one with some cool visualizations, but if we are going to hear it from the horse's mouth so to speak, I will not try to steal y'alls thunder...

Detailed write-ups will appear for sure, but we do want to finish up the final version before we spend the time on those. That said, this effect is reenigne's so he gets the final say on that!

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Reply 6 of 9, by GloriousCow

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VileR wrote on 2023-10-15, 12:21:
My favorite sort of fix. :) Nice! […]
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GloriousCow wrote on 2023-10-14, 23:15:

Well, that's a relief because it's literally a one line fix.

My favorite sort of fix. 😀 Nice!

EDIT: Are any of you guys working on a blog post about the Lake effect? Because it's screaming for one, and I think I am well positioned to write one with some cool visualizations, but if we are going to hear it from the horse's mouth so to speak, I will not try to steal y'alls thunder...

Detailed write-ups will appear for sure, but we do want to finish up the final version before we spend the time on those. That said, this effect is reenigne's so he gets the final say on that!

Ok. I love reenigne's write-ups so I don't want to preemptively spill the beans on how the effect is done, but I do plan an article that at least discusses debugging this interrupt set up chain, from an emulation perspective.
I'm really pleased with this 'video stream' visualization. If you just don't vsync and you keep the edges of hsyncs lined up, you get a nice frame flow.

I took some screen grabs from some of the hardware captures of Area 5150 on youtube that showed at least one 'glitch frame' while Lake set up, and can line them up with the logic analyzer capture:

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area5150 frame flow 01
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I don't know, just cool seeing everything fit like that.

You might be a little curious what i'm doing since doesn't MartyPC run Area 5150 already? All I can say is watch the console output when the end credits start...

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 7 of 9, by reenigne

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My write-up is coming! But yes, we'll publish the write-ups in concert with the final version.
Anybody who wants to is welcome to write about Lake and Wibble. My write-up about these effects will tell a story that nobody else can tell - about how they were developed. A GloriousCow write-up with cool visualizations would nicely complement I think, rather than stealing thunder!

Reply 8 of 9, by GloriousCow

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reenigne wrote on 2023-10-15, 17:11:

My write-up is coming! But yes, we'll publish the write-ups in concert with the final version.
Anybody who wants to is welcome to write about Lake and Wibble. My write-up about these effects will tell a story that nobody else can tell - about how they were developed. A GloriousCow write-up with cool visualizations would nicely complement I think, rather than stealing thunder!

That's certainly a story I want to hear, because the more I dig into this stuff the more inhuman it all seems to be able to accomplish. I can figure out how to emulate it, but I couldn't fathom how to write it in the first place.

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc

Reply 9 of 9, by GloriousCow

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Speaking of visualizations, I think I am going to build something like this into MartyPC as a scrolling event viewer. I was going to do some sort of logic analyzer view, but the extra dimension really comes in handy to see a longer period of time. However, events can overlap...

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area 5150 isr setup timing
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here is Area5150's ISR chain and ultimate effect ISR and starting frames. leading INTR edges are in red with a little glow applied for visibility. yellow lines are INTA bus cycles; pink dots are CRTC updates.

never thought i'd be using photoshop as a log diff tool....

MartyPC: A cycle-accurate IBM PC/XT emulator | https://github.com/dbalsom/martypc