pc2005 wrote on 2023-10-03, 17:32:

A recheck for CPU control signals and specially for cache would be appreciated (my board ATC-1415 has only one cache bank so I could not find control signals for the second one, also it
has only 2 SIMM slots). Some CPU signals are routed through jumpers, so I could miss few.

Thanks for writing up that stuff. I have some notes on that chip, too, which could help you:

151 = /COE (second bank)
258 = /CCE (second bank)
359 = CA0 (first bank or only bank)
461 = CA0 (second bank) or CA1 (single bank)

The way I number the cache address lines, there is no CA1 in dual-bank operation. There are no further /RAS and /CAS pins for four slots. My notes on the Biostar MB-8433-UUD indicate that there are four RAS signals and eight CAS signals.

For memory organization on the 8881, you should be aware that there basically are just two "chipset banks", but each chipset bank (which has a fixed size per rank) can contain up to four(!) memory ranks. In a 4-slot board, there are two pairs of memory slots that need to be equipped with modules with identical bank layout (if both sockets are equipped at all). The chipset can map the chipset banks to

• The first rank of the first slot of a bank
• The first rank of the second slot of a bank
• Both ranks of the first slot of a bank
• Both ranks of the second slot of a bank
• The first rank of both slots of a bank
• Both ranks of both slots of a bank

According to my notes, there is one set of RAS signals (two pins) per chipset bank, one set of CAS signals for the "first slot" of each bank and a second set of CAS signals for the "second slot" of each bank. It seems that your board only populates the first slot of the first bank and the second slot of the second bank, which allows maximum flexibility, as there are no paired slots, and optimal distribution of the load on the /CAS signals. My notes do not indicate anything about /WE for the RAM, but having a second /WE for four-slot systems on pin 170 might be possible, albeit unlikely given that your board already equips both chipset banks and all /CAS signals.

The note about pin 198 (R/W#) having a jumper is likely for CPUs with L1WB. It is usual to connect INVD with R/W#.

pc2005 wrote on 2023-10-03, 17:32:

If you use 486-/PODP-Pinout and Differences as 486 pinout source, careful I think A16 and A13 are swapped there.

Indeed, they are. I already fell into that trap.

Here are my notes on chipset programming registers (no warranty on completeness and/or correctness), includes both the 8881 and the 8886:

1North Bridge
2============
350.80  L2 cache enable
450.40  L2 cache mode (WT/WB)
550.30  Cache read burst (3-2-2-2/3-1-1-1/2-2-2-2/2-1-1-1)
650.08  Two banks of cache
750.07  L2 cache size (none/64K/128K/256K/512K/1024K/resvd/resvd)
8
951.C0  Read WS (3/2/1/0)
1051.30  Write WS (3/2/1/0)
1151.04  A0000-BFFFF(?) PCI write merge
1251.02  Set after memory test, cleared for L1WB
1351.01  Tag allocation (7Tag+1Dirty/8Tag+0Dirty)
14
1552.80  CPU to PCI Post Write (1WS/0WS)
1652.70  bank 2/3 total size (1M/2M/4M/8M/16M/32M/64M/128M)
1752.08  swap banks 0/1 with 2/3
1852.07  bank 0/1 total size (1M/2M/4M/8M/16M/32M/64M/128M)
19
2053.80  CPU to PCI Burst Write
2153.40  Burst copy back option
2253.20  swap bank 2/3
2353.10  swap bank 0/1
2453.0C  bank 2/3 row mode (1*double sided/1*single sided/2*single sided/2*double sided)
2553.03  bank 0/1 row mode (1*double sided/1*single sided/2*single sided/2*double sided)
26
2754.80  DC00 shadow read enable
2854.40  D800 shadow read enable
2954.20  D400 shadow read enable
3054.10  D000 shadow read enable
3154.08  CC00 shadow read enable
3254.04  C800 shadow read enable
3354.02  C0/C4 shadow read enable
3454.01  ESEG shadow read enable
35
3655.80  FSEG shadow read enable
3755.40  Global shadow write protect
3855.20  System BIOS cachable
3955.01  Video BIOS cachable
40
4156.FF  Memory hole base (in 64K blocks)
42
4357.80  Memory hole enabled/disabled
4457.70  Memory hole size (64k/128k/256k/1M/2M/4M/8M/off)
45
4658.FF  0F if system BIOS cachable
4759.FF  00 if system BIOS cachable
48
495A.40  Force cache hit
505A.10  Enable memory parity
515A.02  Some kind of deturbo
525A.01  Cleared during processor clock measurement
53
545C.FF  SMRAM base A27..A20
555D.80  Early Cache Write mode
565D.10  Slow Referesh
575D.0F  SMRAM base A31..A28
58
5960.20  Set when enabling classic AMD SMRAM
6060.02  Disable memory(?) parity

6160.01  Open SMRAM space
6261.C0  EDO mode? (no/resvd/resvd/yes)
6361.08  EDO speed (4-2-2-2/3-1-1-1)
6461.02  Cyrix L1WB mode
65
6662.01  Set on early boot for revision "E"
6762.02  Burst mode (interleaved/linear)
68
69
70South Bridge
71============
7240.10  Set on B2 revision, but cleared if no PS/2 mouse
7340.04  PCI posted memory write
7440.03  IBC devsel decoding (medium/slow/fast/resvd?)
7541.40  Disable parity check (maybe PCI SERR#?)
7641.04  Enhance PCI performance (enabled/disabled) // PCI bus park option (enabled/disabled)
7743.F0  INTA target IRQ
7843.0F  INTB target IRQ
7944.F0  INTC target IRQ
8044.0F  INTD target IRQ
81
8245.04  Set on B2 revision
8345.01  Set on B2 revision, but cleared if no PS/2 mouse
8446.80  PM IRQ (10/15)
8546.40  PM interrupt method (SMI/IRQ)
8646.10  Preempt PCI master option
8746.08  INTD enabled
8846.04  INTC enabled
8946.02  INTB enabled
9046.01  INTA enabled
9147.40  Enable flash writes (0=enabled, 1=disabled). Interop with 57.4 unknown.
9247.08  INTD level triggered
9347.04  INTC level triggered
9447.02  INTB level triggered
9547.01  INTA level triggered
96
9750.80  Set if PCI video BIOS is installed
9850.01  Set by bootblock after 
99
10051.FE  Size of RAM in units of 4M (rounded down, exception: 4M if rounding down results in 0M)
101
10256.80  
10356.60  Cleared by boot block, under some circumstances set by video card setup
10456.0C  KBD clock (7MHz/by4/by3/by2)
10556.03  ISA clock (by3/by4/by2/resvd?)
106
10757.20  Set to flash. For whatever reason
10857.10  Set on B2 revision
10957.08  Keyboard Emulation
11057.04  Some bit used for flash write protection (Guessed: GPO, but seems wrong)
111  8886AF/8886BF: Shuttle HOT433 and Biostar UUD8433: Set = Protected, Clear = Writeable
112  8886F:         Gigabyte GA486IM:                   Clear = Protected, Set = Writeable
11357.03  IO recovery time (2BLCK/4BCLK/8BCLK/12BCLK)
114
11570.80  Monitor PCI4 master activity
11670.40  Monitor PCI3 master activity
11770.20  Monitor PCI2 master activity
11870.0F  Green Timer minutes (0.5/1/2/4/8/16/32/64/128/256/512/rsvd/rsvd/rsvd/disable/0.25)
11971.80  Monitor PCI1 master activity
12071.40  Monitor LPT access
12171.20  Monitor COM access
12271.10  Monitor ISA DMA master access
12371.08  Monitor IDE access
12471.04  Monitor Floppy access
12571.02  Monitor Graphics card access
12672.80  Monitor extra region A9
12772.7E  Monitor extra region mask (1=don't care for A0..A5) Really A0?
12872.01  Monitor VL slave access
12973.FF  Monitor extra region A8-A1
13074.01  Monitor ISA shared memory access (A0000-D0000)
13176.40  Set in flash-related code
13276.30  SMI interface mode (Intel/Cyrix classic/?/AMD classic)
13376.08  Will be set by non-PCI VGA access? Cleared and probed in write-merge setup code
13476.04  Cleared by APM init
13576.02  Set by APM CPU idle, cleared by APM init
136
13782.03  Set on B2 revision to 3
138
13990.08  Wake-Up on IRQ3
14090.10  Wake-Up on IRQ4
14190.20  Wake-Up on IRQ5
14290.40  Wake-Up on IRQ6
14390.80  Wake-Up on IRQ7
14491.01  Wake-Up on IRQ8
14591.02  Wake-Up on IRQ9
14691.04  Wake-Up on IRQ10
14791.08  Wake-Up on IRQ11
14891.10  Wake-Up on IRQ12
14991.40  Wake-Up on IRQ14
15091.80  Wake-Up on IRQ15
151
152A0     Set to 0 by Boot Block
153       Set to 34 by APM init (SMI mask?, 1 = enable)
154A2.01  SMM event 0
155A2.02  SMM event 1
156A2.04  SMM event 2
157A2.08  SMM event 3
158A2.10  SMM event 4
159A2.20  SMM event 5
160A2.40  SMM event 6
161A2.80  SMM event 7
162A4.03  CPU-to-PCI (2:1/1:1/3:2/resvd?)
163
164IDE controller (only on 8886BF)
165===============================
16641.80  Enable primary channel
16741.40  Enable secondary channel
16841.04  Cleared above PCI33
16942.FF  Set to 33 on boot
17043.C0  Something for PM (0=fast, 3=slow)
17143.30  Something for PS
17243.0C  Something for SM
17343.03  Something for SS
17444.F0  Another thing for PM (2=fast, 12=slow)
17544.0F  Another thing for PS
17645.F0  Another thing for SM
17745.0F  Another thing for SS
17846.F0  Third thing for PM (0=fast, 12=slow)
17946.0F  Third thing for PS
18047.F0  Third thing for SM
18147.0F  Third thing for SS
18248-49  just like 44-45
1834A-4B  just like 46-47
184
185
186IO 108, key: 4A/6C (only before 8886BF)
187==================
188B0.40  Enable secondary IDE channel
189B2.F0  Something for PM (0=fast, 4=slow)
190B2.0F  Something for PS
191B3.F0  Something for SM
192B3.0F  Something for SS
193B4.F0  Another thing for PM (3=fast, 12=slow)
194B5.0F  Another thing for PS
195B6.F0  Another thing for SM
196B6.0F  Another thing for SS
197B7.F0  Third thing for PM (2=fast, 12=slow)
198B7.0F  Third thing for PS
199B8.F0  Third thing for SM
200B8.0F  Third thing for SS

mkarcher wrote on 2023-10-03, 18:38:

Here are my notes on chipset programming registers (no warranty on completeness and/or correctness), includes both the 8881 and the 8886:

1South Bridge
2============
341.20 Set during UM8886BF FIFO mode and restored to prior state afterward
4
5IDE controller (only on 8886BF)
6===============================
740.08 Set when secondary interface owns FIFO, clear for primary or FIFO disabled
840.40 Set when FIFO is being accessed using bus mastering, clear otherwise
940.20 Set when FIFO is being accessed using PIO, clear otherwise
1040.10 Set when FIFO is filling, clear when draining or disabled
1141.0F Unknown, set to 0D if north bridge is UM8881N/UM8891N or 09 otherwise
1242.FF Unknown, set to 33 if north bridge is NexGen/UM8881N/UM8891N or 30 otherwise
1354-57 Bus mastering physical memory address
1458-59 Bus mastering number of DWORDs remaining to transfer

The UM8886BF FIFO is 60 bytes in size. There is no intelligence of sector size, multiple sector transfers, ATA vs. ATAPI commands, etc. so the UM8886BF has to be told when to stop reading from the drive by flipping from filling to draining mode at the correct moment, then from draining to disabled when done, on every transfer. This requires changes to the IRQ 14/15 handler. The FIFO cannot just be enabled at boot.

The UM8886BF bus mastering does not support hardware scatter-gather I/O, limiting its utility in a multitasking OS as the driver has to watch register 58h count down to zero before loading the address of the next physical page. There are also alignment restrictions leading to an unaligned head/tail that gets accessed in FIFO PIO or plain PIO mode when doing a bus master read.

The UM8886AF FIFO is 8 bytes in size, and there is no bus mastering, and it doesn't use PCI configuration registers as was already shown above, and doesn't show up as a PCI IDE controller in the list of PCI devices, as if it were a VLB interface.
The IDE portion of UM8886AF was also sold as a discrete UM8673 chip on a PCI card but with jumper configuration: Re: UMC IDE/EIDE controller datasheets
The UM8886F lacks IDE and on some boards, is paired with a CMD640 or other non-UMC PCI IDE chip.

Thanks guys for providing additional informations.

mkarcher wrote on 2023-10-03, 18:38:

[…]
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151 = /COE (second bank)
258 = /CCE (second bank)

Yeah I thought it will be something like this.

mkarcher wrote on 2023-10-03, 18:38:

The way I number the cache address lines, there is no CA1 in dual-bank operation. […]
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159 = CA0 (first bank or only bank)
261 = CA0 (second bank) or CA1 (single bank)

The way I number the cache address lines, there is no CA1 in dual-bank operation.

Is the pin 61 typo? I have VCC on 61. Assuming it is pin 62.

OK so it is similar to SiS496/7. Hmm if I have interlaved cache (dualbank), where do I get CA1 for them? Is it CPU address line 3 (pin 37)? On the single bank configuration the pin 37 is not connected to any cache chip.

mkarcher wrote on 2023-10-03, 18:38:

There are no further /RAS and /CAS pins for four slots. My notes on the Biostar MB-8433-UUD indicate that there are four RAS sig […]
Show full quote

There are no further /RAS and /CAS pins for four slots. My notes on the Biostar MB-8433-UUD indicate that there are four RAS signals and eight CAS signals.

For memory organization on the 8881, you should be aware that there basically are just two "chipset banks", but each chipset bank (which has a fixed size per rank) can contain up to four(!) memory ranks. In a 4-slot board, there are two pairs of memory slots that need to be equipped with modules with identical bank layout (if both sockets are equipped at all). The chipset can map the chipset banks to

• The first rank of the first slot of a bank
• The first rank of the second slot of a bank
• Both ranks of the first slot of a bank
• Both ranks of the second slot of a bank
• The first rank of both slots of a bank
• Both ranks of both slots of a bank

According to my notes, there is one set of RAS signals (two pins) per chipset bank, one set of CAS signals for the "first slot" of each bank and a second set of CAS signals for the "second slot" of each bank. It seems that your board only populates the first slot of the first bank and the second slot of the second bank, which allows maximum flexibility, as there are no paired slots, and optimal distribution of the load on the /CAS signals.

Uh the DRAM topology always make my head hurt. So it is an opposite of SiS496/7, which has 4 CAS and 8 RAS? So basically it is like backported pentium memory controller, where you would need 8 bytes' words to fill 64bit bus. And with this imaginary 64bit SIMM you could use only 2 both side modules?

I think I'm gonna just rename the signals to CAS0-7 and be done with it 😁 .

OT: I guess it could be faster than SiS controller, but if there is really limitation to use only 2 same pair, that sort of sucks 😒 .

mkarcher wrote on 2023-10-03, 18:38:

My notes do not indicate anything about /WE for the RAM, but having a second /WE for four-slot systems on pin 170 might be possible, albeit unlikely given that your board already equips both chipset banks and all /CAS signals.

Yeah most likely UM891 also has a single MWE ... but it means, there is still unidentified pin in DRAM section (would be funny if it was a clock for a secret SDRAM mode 😁 ).

mkarcher wrote on 2023-10-03, 18:38:

The note about pin 198 (R/W#) having a jumper is likely for CPUs with L1WB. It is usual to connect INVD with R/W#.

It seems so. Both of these are located on jumpers near to each other.

There are still some pins not connected on the CPU socket on my board: FLUSH, BS8, BS16, BLAST, PLOCK, PCHK and PWT. but I guess they are not relevant (BSx could be decoded from BEx).

Registers added.

pc2005 wrote on 2023-10-04, 04:26:

mkarcher wrote on 2023-10-03, 18:38:

The way I number the cache address lines, there is no CA1 in dual-bank operation. […]
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159 = CA0 (first bank or only bank)
261 = CA0 (second bank) or CA1 (single bank)

The way I number the cache address lines, there is no CA1 in dual-bank operation.

Is the pin 61 typo? I have VCC on 61. Assuming it is pin 62.

OK so it is similar to SiS496/7. Hmm if I have interlaved cache (dualbank), where do I get CA1 for them? Is it CPU address line 3 (pin 37)? On the single bank configuration the pin 37 is not connected to any cache chip.

I have 61 in my notes, but that may be wrong. I would assume 62 is correct.

Generally, the address bits on the data RAM that select the tag line are directly taken from the CPU. These address bits are also routed to the tag RAM. In single bank cache, there are four data words per cache bank, so two extra address bits are required to select the word in the line. I call those CA0 and CA1. In interleaved cache, only two words are stored per cache bank, so a single address bit is sufficient to select the word inside a bank. I call this single address bit (per bank) CA0. CPU address bits A2 and A3 are not directly routed to the cache RAM. If you expand from 512KB single-banked to 1024KB dual-banked, the pin that was connected to CA1 on the first bank is replaced by CPU A19, which is also routed to the second bank.

Most boards do shuffle the address bits around for ease of routing. For example, the Biostar MB-8433UUD-A routes CA0 to cache A11, and in single bank mode, CA1 to to cache A10. As that board only supports 256K dual-banked, in dual-bank mode, cache A10 is replaced by CPU A17. A11 of the second bank is always connected to pin 62. If the bank is not populated, it doesn't matter that this pin contains CA1. If that bank is populated, though, the pin is reconfigured to be "second bank CA0", which is a perfect fit.

pc2005 wrote on 2023-10-04, 04:26:

mkarcher wrote on 2023-10-03, 18:38:

There are no further /RAS and /CAS pins for four slots. My notes on the Biostar MB-8433-UUD indicate that there are four RAS signals and eight CAS signals.

Uh the DRAM topology always make my head hurt. So it is an opposite of SiS496/7, which has 4 CAS and 8 RAS? So basically it is like backported pentium memory controller, where you would need 8 bytes' words to fill 64bit bus. And with this imaginary 64bit SIMM you could use only 2 both side modules?

I think I'm gonna just rename the signals to CAS0-7 and be done with it 😁 .

Looking at the RAS and CAS signals, this is very much comparable to a Pentium memory controller, indeed. On the other hand, contrary to a Pentium controller, the two SIMMs of one pair use the same data lines, while on the Pentium, they have dedicated lines to fill the 64-bit bus. Also, most Pentium controllers require both sockets to be populated (The SiS 5571 which supports half-populated banks in an exception), while the UM8881 supports single SIMMs in either socket as well as a SIMM pair. There is no need to use "dual-rank" (two-sided) modules for the Pentium variant, as a single side per slot is enough to fill the 64 bits.

pc2005 wrote on 2023-10-04, 04:26:

OT: I guess it could be faster than SiS controller, but if there is really limitation to use only 2 same pair, that sort of sucks 😒 .

The pairs may be different. For example, I can plug an 8MB module in Slot 1, another 8MB module in Slot 2, a 32MB module in Slot 3 and another 32MB module in Slot 4, for a total of 80MB RAM. This will use all 8 ranks. Most SiS boards I've seen only support seven ranks, because they chose a pin multiplexing configuration that doesn't offer the eighth /RAS signal. I can remove any SIMMs I like from that configuration, and all remaining SIMMs will work properly. Of course, I may not remove all SIMMs at once.

pc2005 wrote on 2023-10-04, 04:26:

mkarcher wrote on 2023-10-03, 18:38:

My notes do not indicate anything about /WE for the RAM, but having a second /WE for four-slot systems on pin 170 might be possible, albeit unlikely given that your board already equips both chipset banks and all /CAS signals.

Yeah most likely UM891 also has a single MWE ... but it means, there is still unidentified pin in DRAM section (would be funny if it was a clock for a secret SDRAM mode 😁 ).

The SiS496 has a "/MRE" signal on pin 138, which is used to control data buffers between memory and the CPU (which are optional). The unidentified pin on the UM8881 could have a similar purpose.

pc2005 wrote on 2023-10-04, 04:26:

mkarcher wrote on 2023-10-03, 18:38:

The note about pin 198 (R/W#) having a jumper is likely for CPUs with L1WB. It is usual to connect INVD with R/W#.

It seems so. Both of these are located on jumpers near to each other.

Two jumpers also make sense: Classic Cyrix CPUs want INVD at S4, while the "standard DX4 pinout" has INVD at A10, so routing W/R# to either of these pins using two jumpers would make sense.

pc2005 wrote on 2023-10-04, 04:26:

There are still some pins not connected on the CPU socket on my board: FLUSH, BS8, BS16, BLAST, PLOCK, PCHK and PWT. but I guess they are not relevant (BSx could be decoded from BEx).

BSx can not be decoded from BEx. BS pins are inputs to the CPU, indicating incomplete execution of the cycle due to limited width. If /BS8 is asserted while /RDY is asserted, only the lowest /BEx line has been serviced, and the CPU needs to re-issue the cycle with the lower /BEx line deasserted. If /BS16 is asserted while /RDY is asserted, and /BE0 and /BE1 were asserted in that cycle, only D0-D15 (as appropriate) have been serviced, and the cycle has to be repeated without /BE0 and /BE1 to service D16-D31. If the chipset handles splitting 32-bit cycles int two 16-bit cycles, /BS16 may be left unconnected. VLB exposed /BS16 to make 16-bit graphics chips like the CL-GD542x or the ET4000AX easily connectable, and most early 486 chipsets do not support a 32-to-16-split, so /BS16 is traditionallly used on 486 boards, but this may have changed with PCI-based systems.

VL pins, observed on the Gigabyte GA486IM

• 190 = /LGNT1
• 191 = /LGNT2
• 192 = /LREQ1
• 193 = /LREQ2
• 202 = /LRDY
• 203 = /LDEV

On a VL-less board, I would expect pull-up resistors on both /LDEV and /LRDY. Obviously, 190-193 are multiplexed, being either parity pins or VL master control pins.

I didn't find any new clue for pin 170. The "/MRE#" theory still seems plausible.

mkarcher wrote on 2023-10-04, 05:42:

pc2005 wrote on 2023-10-04, 04:26:

mkarcher wrote on 2023-10-03, 18:38:

The way I number the cache address lines, there is no CA1 in dual-bank operation. […]
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159 = CA0 (first bank or only bank)
261 = CA0 (second bank) or CA1 (single bank)

The way I number the cache address lines, there is no CA1 in dual-bank operation.

Is the pin 61 typo? I have VCC on 61. Assuming it is pin 62.

OK so it is similar to SiS496/7. Hmm if I have interlaved cache (dualbank), where do I get CA1 for them? Is it CPU address line 3 (pin 37)? On the single bank configuration the pin 37 is not connected to any cache chip.

If you expand from 512KB single-banked to 1024KB dual-banked, the pin that was connected to CA1 on the first bank is replaced by CPU A19, which is also routed to the second bank.

Ah OK, that's what I've needed to know, if other CPU address pins are used in caching too. I will probably update the description of the pin to something like:

120; PA19; bidir; CPU/cache/tag address 19/17/15?

No sure if the TAG SRAM in 1 MiB configuration uses this pin also. I used numbering of cache address in description from CPU/chipset point of view I doubt it will be shuffled even in chipset design. Gonna need to look into it later. The numbering I've made seems to be weird anyway for interleaved addresses.

mkarcher wrote on 2023-10-03, 18:38:

Looking at the RAS and CAS signals, this is very much comparable to a Pentium memory controller, indeed. On the other hand, contrary to a Pentium controller, the two SIMMs of one pair use the same data lines, while on the Pentium, they have dedicated lines to fill the 64-bit bus. Also, most Pentium controllers require both sockets to be populated (The SiS 5571 which supports half-populated banks in an exception), while the UM8881 supports single SIMMs in either socket as well as a SIMM pair. There is no need to use "dual-rank" (two-sided) modules for the Pentium variant, as a single side per slot is enough to fill the 64 bits.

Yeah that was just an observation it looks like 64 bit CPU bus HDL backport, where they just multiplexing 32+32 bit data pins into 32 bit bus, but the RAS address would be same for both halves (hmm it could be even faster than addressing RAS separately).

mkarcher wrote on 2023-10-03, 18:38:

Most SiS boards I've seen only support seven ranks, because they chose a pin multiplexing configuration that doesn't offer the eighth /RAS signal. I can remove any SIMMs I like from that configuration, and all remaining SIMMs will work properly. Of course, I may not remove all SIMMs at once.

And even less if HLOCK and BOFF is used instead of RAS5 and RAS6 on SiS496 (but I don't think there is a board which has that). BTW supporting different size is nice 😀 . BTW DOS should fit in 1 MiB L2 cache in CAR mode, so no RAM should be possible too 😁 .

mkarcher wrote on 2023-10-03, 18:38:

... MRE ...

I guess, it make sense, I've added it into the description. I will be most likely output pin (no pull up I think). But I would say, it would be more like /OE, F245 has direction input (which would be controlled by /MWE) and /OE (tristate) (which needs to be active for reading and writing). However it would be nice to get somebody with buffer to confirm.

mkarcher wrote on 2023-10-03, 18:38:

Two jumpers also make sense: Classic Cyrix CPUs want INVD at S4, while the "standard DX4 pinout" has INVD at A10, so routing W/R# to either of these pins using two jumpers would make sense.

I think that's correct. Meanwhile I've traced all jumpers on the board.

mkarcher wrote on 2023-10-03, 18:38:

BSx can not be decoded from BEx

My bad. I was getting confused by different naming.

mkarcher wrote on 2023-10-05, 17:25:

[…]
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• 190 = /LGNT1
• 191 = /LGNT2
• 192 = /LREQ1
• 193 = /LREQ2
• 202 = /LRDY
• 203 = /LDEV

Thanks! I've added it. Do you want them to be numbered from 1 or there is pinmux for 0th?

Updated datasheet attached (detected pin mismatches between N and BF southbridge revisions).

Sadly bad news. My UMC board seems to be not working. Gonna try to measure it with _very_ old scope, but there is high chance I've bought it already half dead (NB seems to be OK, but SB has problems). So the register documentation hacking will take much longer time (worst case: until I find another cheap UMC board).

pc2005 wrote on 2023-10-15, 01:02:

Ah OK, that's what I've needed to know, if other CPU address pins are used in caching too. I will probably update the descriptio […]
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Ah OK, that's what I've needed to know, if other CPU address pins are used in caching too. I will probably update the description of the pin to something like:

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120; PA19; bidir; CPU/cache/tag address 19/17/15?

No sure if the TAG SRAM in 1 MiB configuration uses this pin also. I used numbering of cache address in description from CPU/chipset point of view I doubt it will be shuffled even in chipset design. Gonna need to look into it later. The numbering I've made seems to be weird anyway for interleaved addresses.

In my oppinion, it makes no sense to list which address bit of the frontside bus is connected to which address bit of data and tag RAMs. This is different on each board, and driven by board layout constraints. The only important thing is that all cache RAMs (tag and data) are connected to continous address lines up to the cache size. So with 256KiB cache, CPU A4..CPU A17 need to be routed to all cache chips. With 1MiB cache, CPU A4..CPUA19 need to be routed to all cache chips (in any order). These address bits select the "cache line". The tag only requires a single byte per line, so it needs no further address bits. The data RAMs need to store four 32-bit words per line in single-bank mode, so they need two extra address bits in single-bank mode, which are taken from the chipset outputs CA0 and CA1. In dual-bank mode, each data bank needs to store two 32-bit words per line, so the data RAMs need a single extra address bit, which is CA0_A (aka CA0) for the first bank and CA0_B (aka CA1) for the second bank. The specific cache address pins that are used for the one or two extra address lines from the chipset are also freely chosable by the board designer, and there seems to be no de-facto standard on how to assign them.

On the other hand, documenting the CPU-address-to-cache-address mapping is very useful if you don't want to make a "chipset datasheet", but a "mainboard service manual". As the retro community often has to deal with improperly stored hardware with broken traces, having a mapping to quickly buzz out wheter all address lines from the CPU reach the cache can be a real time-saver while diagnosing broken boards. In fact, my Biostar MB-8433UUD-A arrived in a condition that it crashed as soon as L2 cache was enabled in CMOS setup, and it turned out to be a broken address trace at the cache sockets. It works fine since I bodged it.

On the topic of "chipset datasheet" vs. "mainboard service manual": There also is no standard at all which address line is routed to which IDSEL pin. Every mainboard manufacturer is free to chose their own mapping (and they do). On the other hand, there is a fixed mapping between "device number" selected by the processor and the corresponding address pin driven by the chipset. For the UM8881, this mapping is revision dependent(!). AD8..AD23 are likely directly mapped to "device numbers" 8 to 23 (I know it for sure for AD12..AD15, the remaining ones are extrapolated), whereas the address lines AD24..AD31 map to device numbers 24..31 (the "natural" mapping) on revisions 0..3, but to device numbers 0..7 on revision 4. I found code in the Award BIOS that rewrites the PCI routing table in shadow RAM depending on northbridge revision, and this code remaps these complete set of 8 device IDs. I have one board with the UM8881 rev E that uses AD27..AD29 and exposes the slots as dev 3 to 5. One exception is device number 16, which is hardwired to address the UM8881, I don't know whether it is driven on AD16, too. While the 8886 is device 18 by convention, this is explicitly wired on the board by connecting both the IDSEL pin and the AD18 pin of the UM8886 to the AD18 pin of the UM8881.

mkarcher wrote on 2023-10-03, 18:38:

Most SiS boards I've seen only support seven ranks, because they chose a pin multiplexing configuration that doesn't offer the eighth /RAS signal. I can remove any SIMMs I like from that configuration, and all remaining SIMMs will work properly. Of course, I may not remove all SIMMs at once.

And even less if HLOCK and BOFF is used instead of RAS5 and RAS6 on SiS496 (but I don't think there is a board which has that). BTW supporting different size is nice 😀 . BTW DOS should fit in 1 MiB L2 cache in CAR mode, so no RAM should be possible too 😁 .

pc2005 wrote on 2023-10-15, 01:02:

mkarcher wrote on 2023-10-03, 18:38:

... MRE ...

I guess, it make sense, I've added it into the description. I will be most likely output pin (no pull up I think). But I would say, it would be more like /OE, F245 has direction input (which would be controlled by /MWE) and /OE (tristate) (which needs to be active for reading and writing). However it would be nice to get somebody with buffer to confirm.

Looking at the SiS496 datasheet, they recommend connecting /MRE to the direction control (because you only want to drive the host bus from the memory bus while you are reading), and have that chip permanently enabled (/OE tied to ground). You might run into issues with write data setup time (I didn't check data sheets now) when you use /MWE as direction control for the F245.

pc2005 wrote on 2023-10-15, 01:02:

Meanwhile I've traced all jumpers on the board.

That's actually another great step in making a service manual for your board. May I suggest you split the UM8881 datasheet into two sections: One that is "datasheet-like" and explains the properties of the UM8881 without going into mainboard details, and a second section that is more "application note"-like and details how the UM8881 is used on the ATC-1415. Stuff like "MA0..MA10" are buffered, but MA11 is just resistor terminated is most likely not that way, because the UM8881 requires it, but because A-Trend considered this a good design choice. I'm doubtful about the MA11 idea, though. It is true that most 486 owners back in the day had no use for MA11 (required for 64MB and 128MB SIMMs only, most people preferred to buy a car over buying a SIMM like that, though 😉 ), so adding an extra buffer for MA11 incurs extra costs at a quite low benefit. On the other hand, if someone does require MA11, the chance of having a lot of memory chips on the module (like 36 16Mx1 chips on a 64MB SIMM) is higher than with lower capacity modules. So using MA11 often implies that having a buffer on all memory address lines is a very good idea.

When you are documenting your board, you might also indicate whether the output of the MA0..MA10 buffers are directly connected to the SIMM sockets, or whether there also are resistors for series termination.

pc2005 wrote on 2023-10-15, 01:02:

mkarcher wrote on 2023-10-05, 17:25:

[…]
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• 190 = /LGNT1
• 191 = /LGNT2
• 192 = /LREQ1
• 193 = /LREQ2
• 202 = /LRDY
• 203 = /LDEV

Thanks! I've added it. Do you want them to be numbered from 1 or there is pinmux for 0th?

No, I have no reasons to use the number 1 and 2. The numbers 0 and 1 are equally fine. I also have no reason to assign the lower number to 190/192 and the higher number to 191/193.

Is it possible that UM8881F pin 170 is no connect (NC)?

A few years ago I was repairing one of my socket 3 boards and took this image of the UM8881F pad location without the IC. The pad for pin 170 had ripped off and it doesn't look like pin 170 went anywhere. Or did this pad connect to an inner layer via or trace?

feipoa wrote on 2023-10-17, 12:47:

Is it possible that UM8881F pin 170 is no connect (NC)?

A few years ago I was repairing one of my socket 3 boards and took this image of the UM8881F pad location without the IC. The pad for pin 170 had ripped off and it doesn't look like pin 170 went anywhere. Or did this pad connect to an inner layer via or trace?
UM8881F_pin_170.JPG

The current working hypothesis is that pin 170 outputs /MRE (memory read enable) or a generic memory enable signal, which is only used if the mainboard has a driver chip between FSB and RAM.Standard consumer mainboards don't have this kind of buffer, so pin 170 indeed needs no connection on this kind of board.

mkarcher wrote on 2023-10-17, 14:49:

feipoa wrote on 2023-10-17, 12:47:

Is it possible that UM8881F pin 170 is no connect (NC)?

A few years ago I was repairing one of my socket 3 boards and took this image of the UM8881F pad location without the IC. The pad for pin 170 had ripped off and it doesn't look like pin 170 went anywhere. Or did this pad connect to an inner layer via or trace?
UM8881F_pin_170.JPG

The current working hypothesis is that pin 170 outputs /MRE (memory read enable) or a generic memory enable signal, which is only used if the mainboard has a driver chip between FSB and RAM.Standard consumer mainboards don't have this kind of buffer, so pin 170 indeed needs no connection on this kind of board.

Since the UM8881F Award BIOS has an "alt bit in tag SRAM" option, do you think those choices only mean 7+1 mode or Always Dirty mode, or would 8+0 mode be indicative of ALTER and ALTWE# pins on the chipset? And if so would they be multiplexed with something else or could ALTWE# explain the NC pin?

jakethompson1 wrote on 2023-10-17, 17:48:

Since the UM8881F Award BIOS has an "alt bit in tag SRAM" option, do you think those choices only mean 7+1 mode or Always Dirty mode, or would 8+0 mode be indicative of ALTER and ALTWE# pins on the chipset? And if so would they be multiplexed with something else or could ALTWE# explain the NC pin?

I don't have a strong oppinion on this. Choosing between 7+1 and always dirty is enough to have this option, and in fact we are not seeing a lot of 486 PCI boards with dedicate dirty/alter RAM (The Intel 82420 aka Saturn being the "odd man"), so not implementing an 8+dirty mode can reduce chipset complexity without significant practical impact, so it's possible. OTOH, the direct competitor, the SiS496 does support 8+dirty. So there is precedence for this mode to exist.

My strongest point against the theory that pin 170 is ALTWE# or ALTER is the vincinity of all the RAM pins. I wouldn't expect a dedicated cache pin at that physical location. If I would have to allocate a ALTER and ALTWE# pin on the 8881 pinout, I would likely put them as tertiary function on one of the parity / VL master arbitration pins.

On the other hand, I recently had a private discussion with a VOGONs member that resulted in the idea that you don't necessarily need an ALTWE# pin at all, because you can design a shared ALTWE#/TAGWE#, unless we missed something in that discussion.

quick info (I will read the new comments again later 😁 )

Pin 170 found! thanks to Landau, there is a discussion on retroweb discord. It seems the pin leads to pin 1 T/R of F245 buffers (all 4 U13 to U15) on board Aquarius Systems/BCOM MB-4DUPC .

So I guess the theory of it being read/output enable is correct.

Yoooooooo this is Landau hit me up if you need me to try and probe any-ting

mkarcher wrote on 2023-10-15, 10:19:

In my oppinion, it makes no sense to list which address bit of the frontside bus is connected to which address bit of data and tag RAMs.
...
On the other hand, documenting the CPU-address-to-cache-address mapping is very useful if you don't want to make a "chipset datasheet", but a "mainboard service manual". As the retro community often has to deal with improperly stored hardware with broken traces, having a mapping to quickly buzz out wheter all address lines from the CPU reach the cache can be a real time-saver while diagnosing broken boards.

Exactly. I wanted to know all possible pin uses (so I could write in the description something like CPU/cache/tag address 19/17/15 for the last possible cache address and CPU address 20 for the first line for only normal address functionality).

I was planning to split the datasheet to board manual eventually when I gonna have enough data to declare general pin function (I didn't even think about those VLB pins could be there, TURBO pin identification is basically fortune telling from my board traces 😁)

mkarcher wrote on 2023-10-15, 10:19:

There also is no standard at all which address line is routed to which IDSEL pin. Every mainboard manufacturer is free to chose their own mapping (and they do). On the other hand, there is a fixed mapping between "device number" selected by the processor and the corresponding address pin driven by the chipset. For the UM8881, this mapping is revision dependent(!). AD8..AD23 are likely directly mapped to "device numbers" 8 to 23 (I know it for sure for AD12..AD15, the remaining ones are extrapolated), whereas the address lines AD24..AD31 map to device numbers 24..31 (the "natural" mapping) on revisions 0..3, but to device numbers 0..7 on revision 4. I found code in the Award BIOS that rewrites the PCI routing table in shadow RAM depending on northbridge revision, and this code remaps these complete set of 8 device IDs. I have one board with the UM8881 rev E that uses AD27..AD29 and exposes the slots as dev 3 to 5. One exception is device number 16, which is hardwired to address the UM8881, I don't know whether it is driven on AD16, too. While the 8886 is device 18 by convention, this is explicitly wired on the board by connecting both the IDSEL pin and the AD18 pin of the UM8886 to the AD18 pin of the UM8881.

Thanks I was hoping for this exact info. Gonna need to test the mapping to UM8886 somehow (should be possible to spam config cycles and observe address pins 😁).

mkarcher wrote on 2023-10-15, 10:19:

Looking at the SiS496 datasheet, they recommend connecting /MRE to the direction control (because you only want to drive the host bus from the memory bus while you are reading), and have that chip permanently enabled (/OE tied to ground). You might run into issues with write data setup time (I didn't check data sheets now) when you use /MWE as direction control for the F245.

So the 32bit buffer gonna have DRAM data signals on one side and CPU+UM8881+cache data signals on the second side and if the pin 170 is /MRE, then when in "1" the direction whould go "into" DRAM slots, so the DRAM data pins should be on pins 11 to 18 of 74F245 buffers. The pins 2 to 9 should be 0 ohms to CPU socket, pins 63 to 95 of UM8881 and pins 11-13, 15-19 of cache chips (or 13-15, 17-21 for 32 pin DIP socket). Pin 19 (/OE) of all four of these 74F245 buffers should be tied to ground.

@mr-spain can you check it on your board? (can talk realtime on discord if you need more info where to check).

mkarcher wrote on 2023-10-15, 10:19:

So using MA11 often implies that having a buffer on all memory address lines is a very good idea.

That would required a new buffer chip. I think rest of the buffers' inputs are already used 😁.

mkarcher wrote on 2023-10-15, 10:19:

When you are documenting your board, you might also indicate whether the output of the MA0..MA10 buffers are directly connected to the SIMM sockets, or whether there also are resistors for series termination.

If the board survives my experiments...

mkarcher wrote on 2023-10-15, 10:19:

No, I have no reasons to use the number 1 and 2. The numbers 0 and 1 are equally fine. I also have no reason to assign the lower number to 190/192 and the higher number to 191/193.

OK I will probably renumber it, Mitac schematics seems to number everything from zero, plus it seems weird to have data parity pins going other way.
(hmm it could be decided by analyzing arbitration priority, unless there is some register which flips is, but that's just nitpicking 😁)

feipoa wrote on 2023-10-17, 12:47:

Is it possible that UM8881F pin 170 is no connect (NC)?

A few years ago I was repairing one of my socket 3 boards and took this image of the UM8881F pad location without the IC. The pad for pin 170 had ripped off and it doesn't look like pin 170 went anywhere. Or did this pad connect to an inner layer via or trace?
UM8881F_pin_170.JPG

It is most likely unconnected by design (which also explains the chance it got to be teared off - no thermal conduction outside). Placing a via directly on the pad is considered a bad design. So if you board doesn't have 32bit F245 buffer to DRAM (as it can be seen here) it is really an unused pin.

jakethompson1 wrote on 2023-10-17, 17:48:

Since the UM8881F Award BIOS has an "alt bit in tag SRAM" option, do you think those choices only mean 7+1 mode or Always Dirty mode, or would 8+0 mode be indicative of ALTER and ALTWE# pins on the chipset? And if so would they be multiplexed with something else or could ALTWE# explain the NC pin?

A special dirty data pin would be needed too. Theoretically there can be an unspecified number of alt pin settings (where only an exhaustive check for every board made would (only) approach the certainty ... or just obtaining the official datasheet 😁). But it seems the main use is for /MRE control.

mkarcher wrote on 2023-10-17, 18:02:

I don't have a strong oppinion on this. Choosing between 7+1 and always dirty is enough to have this option, and in fact we are not seeing a lot of 486 PCI boards with dedicate dirty/alter RAM (The Intel 82420 aka Saturn being the "odd man"), so not implementing an 8+dirty mode can reduce chipset complexity without significant practical impact, so it's possible. OTOH, the direct competitor, the SiS496 does support 8+dirty. So there is precedence for this mode to exist.

IMO if one board design would have a dedicated dirty bit SRAM support, it would be those with COAST slot (or with soldered TQFP SRAM chips).

Anyway thanks everyone for help. Another update attached.

pc2005 wrote on 2023-10-22, 23:27:

Anyway thanks everyone for help. Another update attached.

the attachment wrote:

Pin 20 / PA19: TODO does 1MiB interleaved cache use pin for TAG address?

Yes, it does. I connected that trace manually in Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (if your only other option is L2 at 3-2-2-2) to achieve 1MB cache.

I think there will gonna be some setbacks.

It seems my ATC-1415 was already non-repairably damaged when I bought it. After changing RTC chip, which didn't help, I removed all sources of signals from ISA bus (well actually just MSB). Only chipset lines and pull up resistor pack was left. The measurement by a scope (with 1 microsecond per division) looks like this:

From what I'm deducing , there seems to be some fault capacitance, when ISA bus data signals are acting as inputs. The capacitance seems to be slowly charged through pull up resistor. This most likely interfered with RTC and BIOS data signals and randomly failed the POST. By my calculations the added capacitance is between 1-2 nF, however from SiS and ALi datasheets, there should be only 10-20 pF capacitance on ISA data pins. This was also confirmed by measuring ISA data signals on working ALi board, where all transition edges (input, output stage, external driving, H, L ...) were sharp as expected.

Of course all 16 bits of ISA behaves like that, which seems weird, but I don't have any other explanation than the UM8886BF southbridge gone faulty. This sadly limits my documentation efforts to only hardware, until I'll buy another UMC board (ideally dualbank with 4 SIMM slots 😁 ).

(also the same thread on retroweb discord)

P.S. If you encountered same problem and/or you have an idea what is broken or even how it could be repaired. Please add more info 😁. Also if somebody with a scope could confirm, this isn't some weird oddity of UMC and the signals are similarly sharp as one could expect from SiS/ALi implementations.

Port 108h, register B0h, bit 7 is IDE primary channel: 0 = disable, 1 = enable.
Port 108h, value 34h appears to be get out of UMC IDE configuration mode.
This is from monitoring the I/O output done by the Samsung SPC7700LP-W BIOS - it writes 4Ah followed by 6Ch to port 108h, then register to port 108h, then data to port 109h, then 34h to port 10h.
The PCI ID's are 0x10 (AD27) for northbridge and 0x12 (AD29) for southbridge.

A possible northrbridge erratum: Register 55h bit 7 must be E000-FFFF enable, because if I make my emulated UM8881F behave per what the PDF posted her says, pretty much every AMI BIOS for the chipset beeps and hangs on soft reset. Which leaves the question what the purpose of register 54h bit 0 actually is.

Well long story short: Bought another board, added and fixed register descriptions and discovered semidocumentation for UMC SuperIO. 😁

Oh and I almost forget. I've developed a coreboot port for this chipset 😉

Discord thread: https://discord.com/channels/7131124000599572 … 639214095765544
Github repo: https://github.com/pc2005cz/TheUltimate486Upgrade

And entire document how it was done and how you can run the Blender on 486 is attached.