RayeR wrote on 2024-04-25, 21:05:

Hi, coming here from 968VL thread. I'm interested more in Virge /V64+ card as I have PCI donors. What is the current state of PCB stock? Are there available gerber files to make order in JLCPCB myself?

The Virge 325 chip internally has a bugged VL interface and uses some functions of the PCI interface that just aren't available on VL.
There is a chance that these quirks may be bypassed with a CPLD but this attempt currently is halted.
Using the V64+ is no problem.

Ok, I xan use Trio64V+ too. Is there published any pcb design or not yet?

Wait..i'll publishing soon 765VL-000 (a 325VL-Spinoff for trio64V+ VLB ) Give me pleas one or two weeks.

yes, Virge VLB has heavy buggy VLB-Interface ( Trio64V+ has also a bit buggy VLB Interface )

Cirrus Logic CL-GD5426-28 ISA cards are plentiful and cheap, while chips are VLB capable. Might be easier to implement seeing they all have integrated DACs.
Tons of NOS cl-gd5428-80qc-a chips at $8 on alliexpress.

cirrus logic 542x Serie is not comparabel with S3 Trio-Serie
S3 Trio in overall better than Cirrus Logic GD542x and GD542x VLB card is cheap and easy to find. -> it make no sense to make card whit this chip.

But GD542x ISA card is very attractive option.

Sure, as it waited ~2 years, no hurry 😀
I already have one Cirrus VLB with 1MB so I'm interested in S3 with 2 or better 4 MB DRAM.

RayeR wrote on 2024-05-01, 12:38:

Sure, as it waited ~2 years, no hurry 😀
I'm interested in S3 with 2 or better 4 MB DRAM.

Don't get your hopes up on the 765VL for 4MB. As the VLB uses a lot more pins than PCI, because address and data pins are separate, S3 ditched the /RAS pin for the second bank in favour of a pin for the VL interface if the S3 chip operates in VL mode. So it can only access a single bank of 2MB, which is exactly what the 325VL / 765VL supports.

The 765 can be operated in two modes with different pin functions, a legacy mode and a new mode that supports the interfacing with an MPEG decoder. I'm unsure whether the legacy mode on the 765 allows combining VL and 4MB, but a 325VL spin-off will not operate in that mode, because the 325 does no longer support legacy mode.

it is correct, what mkracher wrote. VL Mode and LFB-Mode (Virge supports only new "LFB" )-> max 2 MB, because one RAS output is use as SAUP-input , if chip is running in vl-mode.

Yes, Trio64v+ in legacy mode is capable running with 4 MB and VL-Mode. But ! 4 MB DRAM is on Trio-family is really useless with their RAMDAC with only max 135 MHz pixel clock. (or does someone like interlaced mode? )
Only Virge has gain with 4 MB. Reason: texture memory.

I think 4MB is good for 2D truecolor mode up to 1024x768. And with 60Hz LCD the 135MHz RAMDAC is more than enough...

Madao wrote on 2024-05-01, 09:27:

Wait..i'll publishing soon 765VL-000 (a 325VL-Spinoff for trio64V+ VLB ) Give me pleas one or two weeks.

yes, Virge VLB has heavy buggy VLB-Interface ( Trio64V+ has also a bit buggy VLB Interface )

pleas don't pull request or make issues call on my github site about (empty) 765VL site. Side is empty and i have reserved name"765VL" .
Many file is ready to uploading, but it hasn't high priority.

https://github.com/matt1187/765VL

published

Thank you. When I'll have some more PCBs to manufacture I'll send a batch to jlcpcb. Curently other real-life stuff has higher priority...

Wow, what a wonderfull news. This is one of the projects I definitely must assemble for my 486.
Madao thank you very much for sharing this with whole comunity!

Madao wrote on 2024-05-27, 18:02:

https://github.com/matt1187/765VL

published

JLCPCB after invention of the Madao: 🤑

I am so happy to see this. Thank you mate.

mkarcher wrote on 2022-04-20, 21:15:

...so you certainly wouldn't undo the LZEXE compression, and patch the byte at offset 0x2d2f from 0x75 to 0xEB.

Hm, seems in my case the decompression went differently (UNLZEXE, Version 2.20), I found at offset 0x2d2f value 0x1E instead of 0x75...

Do you know if the other variants of Trio64 works as well without changes on the PCB?

I mean:
- Trio64
- Trio32
- Trio64V2/DX (86C775)
- Trio64UV+ (86C767)

RayeR wrote on 2024-05-29, 05:35:

mkarcher wrote on 2022-04-20, 21:15:

...so you certainly wouldn't undo the LZEXE compression, and patch the byte at offset 0x2d2f from 0x75 to 0xEB.

Hm, seems in my case the decompression went differently (UNLZEXE, Version 2.20), I found at offset 0x2d2f value 0x1E instead of 0x75...

I couldn't find that version. UNLZEXE 0.81 does not work (at least executed with msdos.exe in a windows command prompt) on that file. My trustworthy old UNLZEXE 0.4 did work, and produced a file in which the EXE payload is sector aligned after the EXE header, causing a shift of 0xD0 bytes compared to the offset I quoted in that post. The offset I quoted is correct if you use the generic EXE unpacker UNP. So it is very likely that you need to look at 2dff instead of 2d2f. I get 0x1E at 2d2f with UNLZEXE 0.4 as well.

mkarcher wrote on 2024-05-29, 17:55:

The offset I quoted is correct if you use the generic EXE unpacker UNP

Thanks for the detailed explanation. I used UNP and found the expected Byte at mentioned offset, so patching done 😀

seleryba wrote on 2024-05-29, 12:18:

Do you know if the other variants of Trio64 works as well without changes on the PCB? […]
Show full quote

Do you know if the other variants of Trio64 works as well without changes on the PCB?

I mean:
- Trio64
- Trio32
- Trio64V2/DX (86C775)
- Trio64UV+ (86C767)

only 765

775 is checked, config strap for BUS interface is fixed to PCI.
Trio64 and 32 doesn't work with this PCB, because pcb is designed for Trio64V+ (LFB mode) and Virge. (different Pinout between LFB Mode and Trio64/legacy mode)
Virge DX (375) is also checked, (same result as 86C775 )

Madao wrote on 2024-05-30, 05:23:

775 is checked, config strap for BUS interface is fixed to PCI.
Trio64 and 32 doesn't work with this PCB, because pcb is designed for Trio64V+ (LFB mode) and Virge. (different Pinout between LFB Mode and Trio64/legacy mode)
Virge DX (375) is also checked, (same result as 86C775 )

Thank you for your response.
I have ordered the PCBs and elements, really excited.
One question about BOM - can I use electrolytic capacitors instead of the tantalum ones? I see that on many Trio64V+ boards it has been used like that but I started to wonder if there will be any difference in e.g. image quality. I suppose that the purpose is to filter the power supply to the chip? Is there any cons of doing that?