VOGONS


First post, by skafen

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Hi All,

I've got a PC Chips M912 that's been sat around for several years that was damaged by a much less skilled me trying to cut off and remove the fake cache on it.

I've now got it back out to have a go at getting it going again. Turns out ham-fisted me cut a couple of address/data lines whilst cutting the fake cache packages off. So I first repaired it by patching/mod-wiring the damaged traces and have it running again with all 4 ram banks working correctly. However I cannot get it to see any L2 cache at all. I've soldered in The tag and bank0 sockets so far just to see if I can get it going with 128K including soldering the jumpers that were hard wired for 256K. I have three sets of 32K x8 and a couple of 8K x8 chips for the tag to play with.

I also have a scope and multimeter and I can see activity on all the address/data lines on the cache sockets and see them raise/lower on less active ones when powering up etc. So I believe that hardware wise it is working. But my suspicions are now with the bios.

Mine is running the Amibios with 12/01/1994D release and the D on that makes me wonder if D means disabled??? Also inside the ami-win bios which I've seen on many boards there is no option at all on this one to enable or disable the external cache - only the internal so that doesn't seem right.

I'm aware of the PC Chips M912 BIOS update for Am5x86 and Cyrix 5x86 topic PC Chips M912 BIOS update for Am5x86 and Cyrix 5x86 which is mainly about the award bios but does show a couple of screen grabs of the amibios and none of them plus any others googling do not show this 1994D version - only a 1994, 1995, or 1995X.

So Please can I ask anyone with an M912 that you've not modified or indeed have modified if you have this 1994D version and also if you have the ability to enable/disable the external cache in the bios (even with none fitted).

My bios chip is not socketed currently and I dont have a method currently to rewrite the 27C512 EPROM anyway so really want to confirm this bios is crippled before I go any further any possibly buy a TL866 T48 programmer and maybe a Windbond W27c5612-45Z) as correct me if I'm wrong a standard motherboard hot-flash can't deal with these 27xxx chips - I have a 440BX P3 with a ZIF socket I use for doing 28/29xxx series for bios or PXE boot roms.

Thanks for any help or advice.

James

Reply 1 of 11, by Nexxen

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IIRC you can't populate all the ram slots at once. It is possible but with the right combo and you don't look like you have it.
https://theretroweb.com/motherboard/manual/am … 0c135064858.pdf
Test with just one bank of 72 pins.

Original BIOS is one time program, you can't reprogram it (it was part of the scam).
You should socket it and buy a new chip.
My L2 cache was working when I did the job, even if the BIOS was the OTP version with forced 256KB of (fake) cache.

Are you sure all L2 lines are good?

PC#1 Pentium 233 MMX - 98SE
PC#2 PIII-1Ghz - 98SE/W2K

- "One hates the specialty unobtainium parts, the other laughs in greed listing them under a ridiculous price" - kotel studios
- Bare metal ist krieg.

Reply 2 of 11, by skafen

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Hi Nexxen, thanks for replying to me.

I've got the manual and the ram config is fine. Bank0 is shared between the 30-pins and the edge 72-pin so with the 30-pin bank in use you can only use a single sided 72-pin simm. The middle 72-pin is double banked, so I have 4mb in the 3o-pin sockets as bank0, a double sided 8mb in the first 72-pin and a single sided 16mb in the bank2 72-pin simm for 28mb ram. Tests passed on and old memtest86 v3.2 boot floppy. Also makes no difference to L2 cache if one or all banks are populated.

"Original BIOS is one time program, you can't reprogram it". No its a real TI 27C512-12 with UV Erase window EPROM. I think PC Chips grabbed whatever they had on the day they were building these boards.
I think my next move is to socket it anyway as I've got a dead NIC with a 28 pin socket I can use and that gives me options.

"Are you sure all L2 lines are good?" - As far as I can tell yes. I can see activity on every address/data pin on every chip on both banks, plus chip select and write enable pins etc. I also have downloaded some hi-res photos of front and back of the board courtsey of a another vogons post of someone who also did the fake to real cache procedure to follow the traces on. Their board too worked after adding the cache but I recall they didn't specify what bios they had but i still said 256K cache whatever was installed.

I remembered I have another 486 board with ami winbios and it DOES have the External Cache Enable/Disable in the advanced menu where I would expect it. Its an ALI Chipset so can't borrow it's rom to test etc. But the fact it is missing on this board still makes me very suspicious of the bios being handicapped on the M912.

Cheers

James

Reply 3 of 11, by Kekkula

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Have you verified with program's like cachechk or speedtest that the cache isn't actually working?

Reply 4 of 11, by skafen

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"Have you verified with program's like cachechk or speedtest that the cache isn't actually working?" - Yes absolutely Have Speedsys and cache check v7, amongst others, that's how I know it isn't working. Speedsys memory graphs do not show any speed change whatsoever passed the 8k of the 486 L1 and cache check numbers show same.

James

Reply 5 of 11, by skafen

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I've just dumped the bios from my board using NSSI and it appears totally different to the 1994 one on retroweb. So I still think its bios at this point.

Reply 6 of 11, by skafen

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I've now desoldered the EPROM and added a socket and thankfully it still works so now I have option to replace the bios if I get a programmer and UV eraser or can rig something else to program these chips as I have 3 spare 27C512 removed from old motherboards.

Replaced the CPU with the intended 486DX2-66 to see how well it runs with the two VL-BUS I/O and Cirrus 5428 cards.

Speedsys results... Also shows no L2 Cache 🙁

Reply 7 of 11, by skafen

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I was right. My 19994D bios hides and disables all access to L2 cache.

I bought a TL-8663G AKA (T48) which works great along with a UV eraser box I won for £1.20 on ebay. The UV eraser is pure chinesium, i.e. terrible but does work fine when I hacked off the unfused plug and added a proper UK plug with 3A fuse.

So I flashed the award and 1995 Amibios to my spare and newly wiped 27C512s and first put the AMI 1995 in. It worked without resetting the cmos and in the advanced menu where it should be was the option to enable the external cache and also an option to switch it between WT and WB.

The Award bios which was CHKCPU's lovely J2 version wiht all its fixes. also correctly had the cache options but as we know required a cmos reset.

I verified that sticking back in the 1994D version and clearing cmos did exactly the same, i.e. hide the l2 cache and disable it. So it's a bad version. AVOID IT!

So I'm currently working with the 1995 AMI version for now as I'm most familiar with it and post codes on the board. I also found that I had a dead 32kx8 chip in all three of my spare cache sets after testing them in the T48 which was annoying but further helped the cause. So now I have a verified set of 128K (4x 32k *8) and currently an 8k x 8 tag chip set. It hangs as it attempts to enable the L2 cache now meaning I still have a further problem to resolve yet.

But I took out the tag chip as that is my suspect to see what would happen and it posted fine with the correct 128K cache identified but behaved very slowly and with no l2 cache. So at this point I think the cache chips are fine and on the address and data busses correctly as the busses on this board go through the cache and then to ram and that I may still have some bad connections to the tag chip which did have some damage under the socket when younger ham-fisted me originally removed the legs of the fake cache.

More probing to be done!

Reply 8 of 11, by skafen

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SUCCESS! I've fixed it. On further probing I found A0 address line to be severed on the socket end of the tag chip so ran a mod-wire. Also when I did the initial repairI think I must have been tired because I wired the damaged A1 and A2 pins back to front too with mod wires so that was easily fixed and now it happily boots with 128K of L2 cache.

I'm using my worst set of bits to test currently so have a really horrible set of 25ns 32k x8 Mitsubishi cache chips which wont tolerate anything faster than 3-2-2-2 timing at 25MHz FSB but they do prove that it works. I've ordered some more sockets to populate the second bank on the board and 4x 20ns Alliance cache chips to fill it with so hopefully it will just work when that's done.

Speedsys results below. Note the difference between ram and l2 cache speed in this config is so low speedsys shows the drop on the graph but doesn't report the L2 rate. But cache check etc sees it fine and the machine boots Win95 okay and runs the benchmarks faster with the l2 cache enabled. For instance 3D Bench shows 31.3 vs 33.5 fps and doom gets about 0.6fps faster. Not much but just proves its working for now.

Reply 9 of 11, by skafen

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Final update. I have installed the four new sockets for Bank1 of the L2 cache and added appropriate mod wires for damaged pads and am pleased to say it all works fine with 256K cache. Installed my new Alliance cache I bought and one chip was sadly flakey so will have to go back but had a spare winbond.

This board works with a 16K x8 tag chip for 256K L2 cache so used that instead of wasting one of my now few remaining 32k x 8 chips. Also found the bios gets better memory and cache performance with stability bu leaving the auto config option in the chipset menu.

So I now have a 256K L2 cache working correctly. Photos below of the completed job just before I added some hot glue to to hold the mod wires underneath in place.

Reply 10 of 11, by Nexxen

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skafen wrote on 2024-07-02, 14:51:

Final update. I have installed the four new sockets for Bank1 of the L2 cache and added appropriate mod wires for damaged pads and am pleased to say it all works fine with 256K cache. Installed my new Alliance cache I bought and one chip was sadly flakey so will have to go back but had a spare winbond.

This board works with a 16K x8 tag chip for 256K L2 cache so used that instead of wasting one of my now few remaining 32k x 8 chips. Also found the bios gets better memory and cache performance with stability bu leaving the auto config option in the chipset menu.

So I now have a 256K L2 cache working correctly. Photos below of the completed job just before I added some hot glue to to hold the mod wires underneath in place.

I was sure you had broken traces.
Good to see one more cacheless board go L2! Enjoy!!

PC#1 Pentium 233 MMX - 98SE
PC#2 PIII-1Ghz - 98SE/W2K

- "One hates the specialty unobtainium parts, the other laughs in greed listing them under a ridiculous price" - kotel studios
- Bare metal ist krieg.

Reply 11 of 11, by skafen

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Thanks Nexxen!

The TAG was trickier to work out as its not on the data and address busses exactly as the actual cache chips but was a good learning experience and the eeprom programmer will be ueful for other projects I have.

For it being a PCChips board its actually okay now its up and running with a VLB Cirrcus 5428 and IDE card. Runs DOS apps okay and even Win95 isn't bad on it so quite happy.

Cheers

James