Looking on the retroweb, the board shots aren't great but I think I understand how the clock generator is set up now, the pictures were high enough res that I can make out where the traces are at least.
The ICD2023sc has three pins that are either pulled high or low to select which frequency to run at. Let's ignore the programmable frequency modes that the clock generator can operate in, I don't think it's doing that:
The attachment icd2023sc-stuff.png is no longer available
Currently you've got 25MHz FSB correct? So it should be the 50MHz value since FSB is usually clk divided by 2 for actual CPU FSB:
The attachment icd2023-clocktable.png is no longer available
Zooming all the way into this picture on the retroweb I could just about make out that there are joins between
R40 & R41, which seems to link to S2
R42 & R43, looks like that goes to S1
R44 & R45, looks like that goes to S0
The attachment icd2023sc2.jpg is no longer available
My thinking is that a resistor put at R40 will pull the signal low giving S2 a value of "0", while putting a resistor at R41 will pull it high giving it a value of "1"
The layout doesn't make sense for them all to be + then - in order or whatever, maybe the locations are swapped for convenience of PCB layout.
Can you measure the upper side of the resistors & pads present at the top where you see the silkscreen for R41, just by the pins of that ZIPP video memory. Those should link to either 5V or Ground.
If R44 & R45 are linked, potentially you can just move the resistor from R44 onto R45 and that should give you 33MHz FSB. But it's a good idea to verify this first 😀