pc2005 wrote on 2024-09-20, 10:49:

Oh and I almost forget.

🤣 forget about the best thing?!?!?!?

>Discord thread

🙁 unsearchable, unachievable, undiscoverable

>Github repo: https://github.com/pc2005cz/TheUltimate486Upgrade

Now we are talking.
https://github.com/pc2005cz/TheUltimate486Upg … ob/main/main.md
https://github.com/pc2005cz/TheUltimate486Upg … 486_Upgrade.pdf

This is fantastic! At first glance:

- Eprom with sticky tape (Im surprised you didnt blow anything with it, sticky tape loves generating static electricity) pull handle tells me you didnt investigate eprom emulators 🙁
- eeew AT&T assembly syntax 😐 how does anyone tolerate this madness ?!?!
- rename main.md to README.md
- this deserves own thread

now back to reading, Im barely on page 7 😀

pc2005 wrote on 2024-09-20, 10:33:

Well long story short: Bought another board, added and fixed register descriptions and discovered semidocumentation for UMC SuperIO. 😁

I found this in the current revision of the document:

UMC8881 3rd-party documentation wrote:

Is your cache + TAG address address routing compatible with pin description? My board's manual suggests jumper connection for an address line to TAG RAM pin, which is N/C for the suggested chip size

Are you aware that there are two different pin-outs of 128kBit (16K x 😎 SRAMs? Soyo calls them "Aster" and "Winbond" pinout. The difference between the pinouts is that "Winbond" has A13 (the highest address bit) on pin 26 (which is an active-high chip enable on 8K x 8 SRAMs), whereas "Aster" has A13 on pin 1, IIRC. As there are no datasheets for the Aster RAM to be found easily on the internet, I don't know whether pin 26 of the Aster AE88128AK is CE2 or NC.

...holy carp 🤣. This was a fun read, excellent effort !

Impressive indeed.

mkarcher wrote on 2024-09-20, 17:07:

I found this in the current revision of the document: […]
Show full quote

pc2005 wrote on 2024-09-20, 10:33:

Well long story short: Bought another board, added and fixed register descriptions and discovered semidocumentation for UMC SuperIO. 😁

I found this in the current revision of the document:

UMC8881 3rd-party documentation wrote:

Is your cache + TAG address address routing compatible with pin description? My board's manual suggests jumper connection for an address line to TAG RAM pin, which is N/C for the suggested chip size

Are you aware that there are two different pin-outs of 128kBit (16K x 😎 SRAMs? Soyo calls them "Aster" and "Winbond" pinout. The difference between the pinouts is that "Winbond" has A13 (the highest address bit) on pin 26 (which is an active-high chip enable on 8K x 8 SRAMs), whereas "Aster" has A13 on pin 1, IIRC. As there are no datasheets for the Aster RAM to be found easily on the internet, I don't know whether pin 26 of the Aster AE88128AK is CE2 or NC.

I have an Aster tag SRAM somewhere if I can find it. Is there any way to tell that using a multimeter to measure resistance between pins, etc. or it really needs to be the datasheet?

jakethompson1 wrote on 2024-09-21, 00:40:

I have an Aster tag SRAM somewhere if I can find it. Is there any way to tell that using a multimeter to measure resistance between pins, etc. or it really needs to be the datasheet?

You can try whether the chip works with pin 26 grounded (pin 26 is "NC") or it only responds with pin 26 high (pin 26 is "CE2"). You would need some kind of test rig for that, though. Devices like the Retro Chip tester or the TL866 contain the necessary hardware for being a universal test rig, but I'm afraid I don't know how easy it is to get the hardware to "test a 16k x 8 SRAM with A13 on pin 1 and pin 26 grounded". Typically, the included software only has fixed patterns that are not meant to be customized by the user.

rasz_pl wrote on 2024-09-20, 16:21:

>Discord thread
🙁 unsearchable, unachievable, undiscoverable
- this deserves own thread

Yeah I've started this one. Yeah discord links are weird, are you on the retroweb server?

rasz_pl wrote on 2024-09-20, 16:21:

This is fantastic! At first glance:
- Eprom with sticky tape (Im surprised you didnt blow anything with it, sticky tape loves generating static electricity) pull handle tells me you didnt investigate eprom emulators 🙁

😁

mkarcher wrote on 2024-09-20, 17:07:

Are you aware that there are two different pin-outs of 128kBit (16K x 😎 SRAMs? Soyo calls them "Aster" and "Winbond" pinout. The difference between the pinouts is that "Winbond" has A13 (the highest address bit) on pin 26 (which is an active-high chip enable on 8K x 8 SRAMs), whereas "Aster" has A13 on pin 1, IIRC. As there are no datasheets for the Aster RAM to be found easily on the internet, I don't know whether pin 26 of the Aster AE88128AK is CE2 or NC.

Ah interesting I don't think I've seen Acter chip Makes sense then, thanks. It shouldn't be a difference from the northbridge point of view (as it is rerouted by a jumper ... also ATC-1415 was a weird board 😁).

How was E000-EFFF determined to be controlled by register 54th bit 0? That seems to contradict my observation of AMI BIOS'es breaking.

Edit: Nevermind, with the new documentation, this actually works correctly!

dear friend，I got a dx-9200i，which have 4 simm and 8 fake cache 1 fake tag. can I do some test to conteibute for you?

youxiaojie wrote on 2025-01-16, 16:56:

dear friend，I got a dx-9200i，which have 4 simm and 8 fake cache 1 fake tag. can I do some test to conteibute for you?

https://theretroweb.com/motherboards/s/pcchips-m915i

I wonder what likelihood there would be to make a Pentium version of this as well, using the UMC UM8890 northbridge (the southbridges are the same as for 486)?

Battler wrote on 2025-02-06, 02:01:

I wonder what likelihood there would be to make a Pentium version of this as well, using the UMC UM8890 northbridge (the southbridges are the same as for 486)?

It should be easier as posted earlier in the thread: Re: UMC8881/8886 Datasheet

youxiaojie wrote on 2025-01-16, 16:58:

youxiaojie wrote on 2025-01-16, 16:56:

dear friend，I got a dx-9200i，which have 4 simm and 8 fake cache 1 fake tag. can I do some test to conteibute for you?

https://theretroweb.com/motherboards/s/pcchips-m915i

Yes of course, you can! 😀

By the way are you planning to use coreboot too? It would need to add your board into the build tree. If you know embedded C it shouldn't be that complicated. But problem is your board doesn't have an integrated COM port and coreboot heavily uses them for debug. It should be possible to add an ISA card with them though (not sure if you need to set up some register in the chipset).

Anyway even if you are not planning to use coreboot you can always help. Does your board have stickers on the chipset? If you are OK to removing them or it doesn't have any. You could make a readable photo of the part numbers (so we can have some information between part numbers and register set, as in "Revisions" section of the reversed datasheet).

If you have "Exx" revision (EDO support) I can always have more data for unusual RAM configurations. Especially if you have SIMMs with 12 address bits (64 MiB or 128 MiB per stick).

If you have non EDO revision. Even better! I have no information about what registers were added at which chipset revision. But it gonna need a lot of measuring 😉.

You can send here dumped registers from any PCI config space DOS utility. For example this one. If you run it from MSDOS (so there is no windows driver interference), you can save the obtained data to a file file and post it here.

Also I wonder, as your board doesn't have LPT+COM, does it show ports in the pre-boot BIOS report table if an ISA COM/LPT card is installed?

Battler wrote on 2025-02-06, 02:01:

I wonder what likelihood there would be to make a Pentium version of this as well, using the UMC UM8890 northbridge (the southbridges are the same as for 486)?

If you have a board you can just identify the registers by iterating over different BIOS options permutations and by different configuration. I've tried to disassemble BIOS in ghidra, but I didn't need it in the end (maybe only for superIO unlock access, but then I've found it was documented in some of the mobo manuals). Of course most of the documentation was already gathered from other people 😉. Doing it completely from zero would be tiring, even just fixing RAM configuration description took many combination of RAM sticks and reboots was hell (put a SIMM into slot, power on, boot MSDOS, dump PCI config space, power down, move same SIMM into a different slot, power on, repeat...).

Obviously there may probably be more registers as the platform is newer generation (for example, there could be new bits for controlling the second chipset, pipeline L2 cache settings - or any cache - pentium has different protocols, probably more PCI bus configuration). But if there isn't any bit "lock configuration before booting" it should be possible to eventually make another reversed documentation. If there is bit which makes some registers hidden (for example SMM) the documentation cannot be created by this method.

Does anybody have a UM889x board here? I don't think I ever saw any auction and retroweb has only like 10 boards. I don't think it would be possible to make any documentation without physical access (and only disassembling BIOS images).

BTW those mitac documents seem to have an N variant of the chipset and for the southbridge it seems there is a different pinout. It is highly possible same will be for the northbridge too (multimeter and continuation tester to the rescue - you'll definitelly need a physical access for that 😀 ).

pc2005 wrote on 2025-02-07, 00:46:

Does anybody have a UM889x board here? I don't think I ever saw any auction and retroweb has only like 10 boards. I don't think it would be possible to make any documentation without physical access (and only disassembling BIOS images).

I have two (IIRC) GA-586AM with 8891B. They come up once in a while. There is an over-priced one on ebay now but maybe set a saved search. I mainly got it so I could play with the bus mastering capability on the 8886 IDE that I don't think is on the earlier revision on the 486 boards I have. I also have a NEC Versa laptop with 8891BN. The IDE part of the southbridge was also sold as a discrete UM8673 chip, like this: Re: UMC IDE/EIDE controller datasheets

pc2005 wrote on 2025-02-07, 00:46:

BTW those mitac documents seem to have an N variant of the chipset and for the southbridge it seems there is a different pinout. It is highly possible same will be for the northbridge too (multimeter and continuation tester to the rescue - you'll definitelly need a physical access for that 😀 ).

Oh, sorry. N=notebook, correct? Any idea what the differences would be; presumably something power management or otherwise laptop related?

8886 IDE that I don't think is on the earlier revision on the 486 boards ... Any idea what the differences would be; presumably something power management or otherwise laptop related?

Late 486 may have 8886BF, which does have a nonstandard IDE busmaster. It may be possible 8886N version have even more improved controller. I've found few different pins (keyboard) but I didn't bother to make pinout (the chip was dead and the southbridge doesn't have much configuration options). I agree there will be most likely changes for power management.

Anyway I don't planning to work on UMC chipset for pentium. I have like 5 boards with 486+PCI and I've ported coreboot for only like 1.5 of them so far. However anyone can try 😉

pc2005 wrote on 2025-02-07, 00:22:

Yes of course, you can! :-) […]
Show full quote

youxiaojie wrote on 2025-01-16, 16:58:

youxiaojie wrote on 2025-01-16, 16:56:

dear friend，I got a dx-9200i，which have 4 simm and 8 fake cache 1 fake tag. can I do some test to conteibute for you?

https://theretroweb.com/motherboards/s/pcchips-m915i

Yes of course, you can! 😀

By the way are you planning to use coreboot too? It would need to add your board into the build tree. If you know embedded C it shouldn't be that complicated. But problem is your board doesn't have an integrated COM port and coreboot heavily uses them for debug. It should be possible to add an ISA card with them though (not sure if you need to set up some register in the chipset).

Anyway even if you are not planning to use coreboot you can always help. Does your board have stickers on the chipset? If you are OK to removing them or it doesn't have any. You could make a readable photo of the part numbers (so we can have some information between part numbers and register set, as in "Revisions" section of the reversed datasheet).

If you have "Exx" revision (EDO support) I can always have more data for unusual RAM configurations. Especially if you have SIMMs with 12 address bits (64 MiB or 128 MiB per stick).

If you have non EDO revision. Even better! I have no information about what registers were added at which chipset revision. But it gonna need a lot of measuring 😉.

You can send here dumped registers from any PCI config space DOS utility. For example this one. If you run it from MSDOS (so there is no windows driver interference), you can save the obtained data to a file file and post it here.

Also I wonder, as your board doesn't have LPT+COM, does it show ports in the pre-boot BIOS report table if an ISA COM/LPT card is installed?

perfect! I wanna to testing gentoo and archlinux32, coreboot is perfect!

the dx-9200i I own is not edo support, debug card loops, and octeck 12 vip is edo supported.
I try to take some picture and take a multimeter to trace the route.

I try to dump registers.

perfect! I wanna to testing gentoo and archlinux32, coreboot is perfect!

the dx-9200i I own is not edo support, debug card loops, and octeck 12 vip is edo supported.
I try to take some picture and take a multimeter to trace the route.

I try to dump registers.
and I can read C code and modified some code, I want to try embedded C.
is the edo-support decided by bios or chipset?
does the bios update bring me edo support?

pc2005 wrote on 2024-09-20, 10:33:

Well long story short: Bought another board, added and fixed register descriptions and discovered semidocumentation for UMC SuperIO. 😁

I remember the document attached also contained 8886 pin definition before, but now I could not find.could you add it at free time? thanks!