VOGONS


First post, by BitWrangler

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Hi folks,

I have this ECS 386L ver 1.1 that resurfaced again recently. I had been rather discounting it, not regarding it as board worth bothering with, due to no cache.... then two things happened, I read something about 386 zero wait state memory access modes, realising that for certain CPU it might be fairly decent then. Then secondly, I realised I had two "Full AT" desktop cases in 5170 style, clone not IBM, and that I only had a plan to fill one of them, which is with 286 parts, but nothing assigned to the other. I already have a similar style but not quite so wide case assigned to an "early-ish" 486DX build which most of the parts are original to, so didn't want another 486 in one of that era. I might then give this board a checking out and do something with the flavour of an 88-90 386.. Though maybe this board got itself built inconveniently late in 1992, but it's not that dissimilar from very late 80s boards.

Retroweb page for board https://theretroweb.com/motherboards/s/ecs-386l

I don't wanna say this is a pure "Wing Commander" build, but it's certainly a consideration that it is of that time. The cusp when PC went from business appliance type aesthetics to more home office friendly, and became a family PC. This having then one foot in the past with it's case style and one foot in the future with the game(s) that made everyone notice VGA/386 as a gaming/entertainment platform. Anyway, it will go where it goes, but WC might swing a decision or two.

CPU? It has not got one, nor you may notice, a clock oscillator. All the other pics show 50Mhz for clock halved 25Mhz operation. I might reasonably therefore just put a 25Mhz i386 in it... yawn. I was going to install a clock socket anyway rather than directly mount one. Some examination of the Topcat specifics will be required, my intent is to get it running at 0ws, if that can be done at 33Mhz, I want 33Mhz...Then there's a little voice in my head with a fascination for the 386/486 upgrade CPUs and wants me to stick one of those in it, and represent it as an upgraded 386 trying to take on the 1990s... hmmm. I have no PGA132 chip at all to try in that hole though, so I've gotta hope it will get going if I buy something.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 1 of 6, by douglar

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You want 0 waitstate operation at 25Mhz ? That would require 40ns simms, yes? Fastest I've ever seen is 45ns and I only found 2 of them. But you never know. Sometimes you find magic chips that exceed their specs.

Your best upgrade might be to grab a Cyrix 486DLC. Those are available and your board may be MR BIOS eligible, which would help with the Cyrix support:
https://docs.google.com/spreadsheets/d/1vtPso … #gid=1809868176
Might be worth checking out V019B301 .

Reply 2 of 6, by BitWrangler

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Hmmm yeah, I was wondering if the 4 way interleave and some "small buffer we're not actually calling it cache" inside the chipset would alleviate the access time requirements, since it would seem the mem controller can fire one request off, and have that chugging along a couple of cycles while it does another. Meaning I guess that for an atomic single cycle, zero wait state is a lie, but effectively en masse, it has same effect. Orrrrr, they claimed something it could only realistically do with a bottom of the barrel 12Mhz CPU at the time of design when 80ns RAM was fast.

Thanks very much for the MR Bios deets. I am wondering if this BIOS might be late enough to be Cyrix aware.

I was thinking of the multiplied chips, and having imperfect support, like the upgrade modules/cards, since I thought it would be cool to have a 25Mhz "486" which performs about like 386-33, then when you run the cyrix util the multiplier and enhancements kick in and you get dx2-50 and approx 486SX33 performance.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 3 of 6, by douglar

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I did some tests a couple years back for a 40Mhz 386 & 486DLC running w/ cache or without.

Re: 486DLC cache coherency blues and headaches

TLDR:

  • MR BIOS 1.65 detected the Cyrix chip, but I had to use cyrix.exe at startup to get best performance
  • Doom likes fast memory more than synthetic benchmarks like speedsys
  • A Ti486DLC with just the onchip cache performed about the same as a 386 with a 256MB motherboard cache
  • Had to use the "barb" cache coherency method to make the Cyrix cache work with my motherboard cache
CPU        Mobo   Cyrix    Doom    Speedsys   Read   Write   Move    Avg
Cache Cache Realtics CPU Index MB/s MB/s MB/s MB/s
Ti486DLC 256KB Enable 6830 10.29 30.63 37.48 25.53 31.21
Ti486DLC 32KB Enable 7616 10.20 30.54 37.47 25.48 31.16
Ti486DLC No Enable 10550 9.88 18.57 37.05 13.48 23.04
AM386-40 256KB N/A 10600 6.88 25.53 30.07 38.30 31.30
AM386-40 32KB N/A 11140 6.88 25.47 30.05 38.16 31.23
AM386-40 No N/A 23654 5.19 16.53 29.87 16.49 20.96
Ti486DLC No Off 25448 5.76 18.57 37.05 16.49 24.03

Reply 4 of 6, by BitWrangler

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Very good info, thanks.

Thought I better look see what was actually sitting in it right now in terms of RAM. I am 99.9% sure that's the modules that were sitting in it when I bought it, and it had no CPU then either. I'm a bit foggier about the clock module, whether I "borrowed" it or not. Anyway it arrived to me, definitely prior to 2005, probably prior to 2002. Now one module, has late 1997 marked chips on it, so someone was upgrading or repairing it in 1998, so not all that long before it ended up with me really. Well, I was just assuming it had eight single megabyte chips in there, though at the latest look I had a suspicion that one bank was 4MBs just from general looks. Bank 1 is a nice matched set of NEC 4MB 60ns, Bank 0 is a mishmash of 2 hynix 60ns, one micron 60ns and one with F with a bar over and under it, 70ns, all 4MB. ThirtyTwo MB! Was some madlad trying to put win98 on this thing??? At todays reinflated prices that's a few bucks worth of RAM. I was thinking it might get 16 if I was feeling generous. Not sure what the F is, Fairchild ??

So basically 60ns RAM installed as last working... maybe the 70 kept up, maybe it didn't work and got it retired.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 5 of 6, by BitWrangler

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I may not be pursuing use of this board in the very near future, gonna stick it back in "cold storage" as it were. Leave it to chance as to whether I get an Intel or other CPU for it. This is due to this "unplanned purchase" which kinda eats my "money I thought it was sensible to spend on 386 crap" for a bit and also, although these are more SX, they might be same performance as what I was gonna do here, Re: Bought these (retro) hardware today

Those are also scratching this itch..
AMD 386SX25 or other speeds, PQFP-100, how well do they overclock?
Which I was gonna try to scratch with a DX40/486 combo board which is more like a 2/3 or 3/4 baby AT so not as small.... and haven't turned up that 25mhz half baby AT yet, which I may want to have handy when those others arrive, for comparisons, possible part borrowing and all that.

Anyway, that leaves me kind of wondering what out of all that, if any, suits the full AT format 5170 style case. Though I do have a suspicion that that half baby AT board is hanging out with a 20Mhz 286 board, so that might be Super286 fodder. Has everyone lost track now? Yeah me too, I have to look back at these posts to figure out where I was going, breadcrumbs or something.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 6 of 6, by BitWrangler

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In trying to get clues about the NEAT chipset and the function and malfunction thereof, because of NEAT chipset memory problem on PB800/900 rev D 286 board.... I happened to come across the DTK tech-1234 manual for their NEAT implementation... here http://www.dosdays.co.uk/media/286/DTK%20TECH … rs%20Manual.pdf
Which to me, seemed to read as if during the 286/386 era, manufacturers absolutely intended interleave to be required for the zero wait state mode of their chipsets.

Anyway, I am taking this as evidence that period claims of "zero wait state" are for averagely zero, needing interleave rather than single cycle zero wait state.

It's still in limbo whether project full AT Case = project TOPCAT or not and nothing has materialized on the CPU for it front, which I am kind of leaving to chance rather than pursuing right now.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.