Are you able to double check that 64K also doesn't work with the MR BIOS? Memory has a tendency of twisting results around.

I am able to, but you know my situation. It'll be months before it actually happens.

It's a good thing there's no deadline on any of this.

I'm working on a similar board right now and was able to get 256K working using some 64kx4, DIP28 SRAM modules. 8 for the data and 3 for the tags. I have it working at 80 MHz with an SXL2, but the performance isn't great compared to other boards, e.g. DOOM=17.9 fps, while on UMC 481, it gets 20.1 fps.

My board is the Biostar MB-1333C-CH, but I've installed an 80 MHz oscillator in U27, which presumably turns it into the MB-1340C-CH. However, the northbridge on this board is stamped 33 MHz.

Does anyone know what the DIP14 crystal oscillator next to the 66.667 MHz crystal is for? It reads 32.000 MHz. On my other (dead) Peak/DM board (FU340), the silkscreen under the 32 MHz crystal location says 40 MHz. That dead board, however, came with an 80 MHz primary crystal and it is stamped "40 MHz" on northbridge chip. Thus, I'm wondering if I need to swap both the 66 and 32 MHz crystals when upping the frequency to 40 MHz FSB, e.g. to 80 and 40 MHz for full speed?

There are also some factory soldered shut jumpers on this board, J43, J40, and J44.

On my board:
J43: 2-3
J40: 2-3
J44: 1-2

I could not find any documentation on these jumpers. Are they somehow related to setting the FSB for timings, or related to that 32 MHz crystal?

The second crystal:
I believe there is a BIOS option for selecting ISA Bus Clocks. One of the options is "ATCLKIN" .That should be the second crystal. A 32Mhz crystal gives either a 16Mhz or 8Mhz ISA Bus Clock.

I haven't tested this on my board but wrote it as a note.

This is an excerpt from the Peak DM chipset manual:
"[...]The 82C351 bas a flexible clock selection system as shown in Figure 1-2. This
system generates clocks for both the processor and the AT bus. The inputs to
this clock selection logic are CLK2IN and ATCLKIN. CLK2IN is driven from
a packaged oscillator circuit running at twice the 386DX rated frequency.
ATCLKIN, if present, is usually 16MHz, to provide an 8MHz AT bus clock.[..]"

MikeSG. Thanks for your reply. When discussing with another member, it became clear to me that the 32 MHz crystal was for the fixed 8 MHz ATCLK option when selecting the ISA frequency. This also explains why some boards don't have this crystal, rather, they are just using the standard divisors to derive all ISA frequency options.

PEAK/DM is supposed to support DRAM bank interleave, but the option to enable/disable is hidden in my AMIBIOS. I tried to enable it on my board using amisetup299, but I just makes an unstable system. Anyone else tried this out with different results?

Anonymous Coward wrote on 2024-11-24, 08:34:

PEAK/DM is supposed to support DRAM bank interleave, but the option to enable/disable is hidden in my AMIBIOS. I tried to enable it on my board using amisetup299, but I just makes an unstable system. Anyone else tried this out with different results?

There are two bank interleave options, one is to enable it, the other is to tell it which banks. I tried just to enable it, but left the other option alone. I could not POST with my SCSI card installed. Then I tried to enable, and tell it bank 0 and 1, but the issue was the same - I could not POST with SCSI card installed.

The board's L1, L2, DRAM read speeds match that of other top contenders in the ISA 386 realm, but the write speeds are crap. Unless we find a way to improve upon the write speeds, I think these Peak/DM boards are rubbish. Unfortunately, I did not see a config file for this chipset from CTCHIP34. Also, there are w/s options for the memory in the BIOS, but I see no difference in DOOM results between 1ws, 2ws, 3ws, and 4ws. Were you able to confirm this as well?

I didn’t play with the wait state options, but maybe I’ll pull the board out again to test the sxl2-80, since that chip doesn’t like my FTDI board.

I think it should be possible to create a ctchip34 config file since the chipset Manual contains detailed register programming.

My theory about the bank interleave not working is that there must be some required wiring not present on our boards, and/or hardware bugs that prevent that feature from working.

Could you link to where you found the chipset datasheet for 351, 355, and 356?

SXL2-80 should work fine, just ensure you have "Force RAS High" enabled, otherwise HIMEM errors. only use 9-chip memory modules.

feipoa wrote on 2024-11-24, 11:26:

Could you link to where you found the chipset datasheet for 351, 355, and 356?

http://www.bitsavers.org/components/chipsAndT … elim_199102.pdf

uff, my memory isn't doing great. I already had the chipset databook for this series, albiet the file size is 1 MB different, so I guess there's some difference between them.

Looking through the chipset documentation, I see that the BIOS option which is titled, "Read/Write Cycle Wait State", isn't referring to DRAM timing, rather, it is referring to wait-states being added between the DMA controller and the SCLK input.

On the other hand, wait-states for DRAM timing read/write are located in 82C351, indexes 11h thru 18h. The wait-state options are 3, 4, 5, or reserved, however the documentation states that 5 ws is default. From what I could discern, the BIOS does not have an option for these register indexes.

Does anybody know how to use the DEBUG command to read 82C351's register indexes 11h thru 18h? The databook sheet mentions, Index Register accesses are through l/O ports 22 and 23. This port is active only if index 2B bit 6 is a 1. Similarly, how is debug used to write to these indexes?

Seems strange that AMISETUP also doesn't mention these DRAM wait-states. If the BIOS is already setting the DRAM wait-states to 3ws, then I guess it's already maxed out.

Thanks!

The RAS Precharge Time & CAS Pulse Width might determine DRAM wait states.

My board isn't working so I can't confirm. On my C&T 386sx, CAS extend gave a delay to the DRAM without giving a full wait state.

If the DRAM wait states are fixed, the CAS Pulse Width will add/reduce waits. Don't know about RAS Precharge Time.

DRAM Wait-states, RAS Precharge Time, and RAS Pulse Width are all distinct settings in the Configuration Control Registers. The BIOS has all but the DRAM wait-states as a user adjustable option.

The BIOS also has the following settings, which I could not locate a Configuration Control Register for: CAS Pulse Width and Early CAS Mode. It is possible that these two settings are the missing DRAM Wait-states, or they are just another timing setting. Running some tests with cachechk, I discovered:

Decreasing RAS Precharge Time from 6 to 3 CLK2s, results in a DRAM Write increase from 27.7 MB/s to 33.3 MB/s.

Enabling Early CAS Mode results in a DRAM Write increase from 33.3 MB/s to 55.4 MB/s, but only when you've decreased the RAS Precharge Time.

Decreasing CAS Pulse Width from 6 to 4 CLK2s, results in a DRAM Read increase from 20.8 MB/s to 23.8 MB/s. Setting it to 3 caused no POST.

EDIT:
I also replaced my 351 northbridge with a unit marked "40 MHz", hoping it will enable operation at 85 MHz...

Wow those are some big gains.

C&T are innovators so I figure they use fine tuning like this ... RAS and CAS are definitely for DRAM.

DRAM read speed / CAS Pulse may be the only thing you need to detune when going for higher clocks. Or using faster DRAM.

Did the modified settings close the benchmark gap with your other 386 boards?

Anonymous Coward wrote on 2024-11-26, 06:06:

Did the modified settings close the benchmark gap with your other 386 boards?

Not really. I suspect we'll need to adjust that DRAM timing wait-state to close the gap any further. I suspect this board is run at the default DRAM 5 ws.

Some comparative results with stable timings, all with SXL2-80 and ISA @ 13.3 MHz:

DTK PEM-4036YB
Symphony 461 / 362
DOOM = 21.76 fps

Chaintech 340SCD
SiS 310 / 320 / 330
DOOM = 19.65 fps

MS-3131
UMC 481 / 482
DOOM = 18.52 fps, however I have some older notes indicating 20.8 fps.

Biostar MB-1340C-CH [the board in question]
Peak/DM CHIPS 351 / 355 / 356
DOOM = 18.32 - 18.82 fps. This range exists because on different days, or different uptime durations, I get different results with the same BIOS settings. 18.8 fps is the warmed up final result.

I'm not sure what is going on with the timer on my Peak/DM board. The 32.768 KHz square-wave going into the peripheral controller (82C356) looks OK on the scope. Upon reading the Peak/DM databook, it looks like the two (or 3?) counters and real-time clock are derived from this 32.768 square-wave. There's probably no temperature compensation. Temperature would explain why the DOOM and cachechk numbers stabilise after sufficient uptime.

You can also get a little boost in HDD performance by increasing the 16-bit I/O wait-state from 3 ws (default) down to 1 ws. DOS benchmarks went from 3364 KB/s to 4510 KB/s. Reducing it to 0 ws causes no-POST.

I created a little config file for CTCHIP34, calling it CHIPS351.cfg. I'm not sure if it is correct, maybe someone can verify?

1;**************************************************************
2;Peak/DM CHIPS
3;CPU/Cache/DRAM Controller: 82C351, Bus: 82C355, Peripheral: 82C356
4;**************************************************************
5
6;************** 82C351 *******************
7MACRO OPEN =2bh:x1xxxxxx
8MACRO CLOSE=2bh:x0xxxxxx
9INDEXPORT=22h           ;address port
10DATENPORT=23h           ;data port
11;******************************************************************
12
13INDEX=11h       ; Block 0 RAM timing (Read/Write)
14BIT=76          ; DRAM wait states
15		00= 3 ws
16		01= 4 ws
17		10= 5 ws
18		11= Reserved
19
20BIT=5           ; Reserved - write 0
21		0= unknown
22		1= unknown
23
24BIT=43          ; -RAS <0:1> Precharge time
25		00= 4 CPUCLKIN cycles
26		01= 6 CPUCLKIN cycles
27		10= 8 CPUCLKIN cycles
28		11= 8 CPUCLKIN cycles
29
30BIT=21          ; -RAS <0:1> Refresh pulse width
31		00= 4 CPUCLKIN cycles
32		01= 5 CPUCLKIN cycles
33		10= 6 CPUCLKIN cycles
34		11= 7 CPUCLKIN cycles
35
36BIT=0           ; Reserved - write 0
37		0= unknown
38		1= unknown
39
40INDEX=13h       ; Block 1 RAM timing (Read/Write)
41BIT=76          ; DRAM wait states
42		00= 3 ws
43		01= 4 ws
44		10= 5 ws
45		11= Reserved
46
47BIT=5           ; Reserved - write 0
48		0= unknown
49		1= unknown
50
51BIT=43          ; -RAS <0:1> Precharge time
52		00= 4 CPUCLKIN cycles
53		01= 6 CPUCLKIN cycles
54		10= 8 CPUCLKIN cycles
55		11= 8 CPUCLKIN cycles
56
57BIT=21          ; -RAS <0:1> Refresh pulse width
58		00= 4 CPUCLKIN cycles
59		01= 5 CPUCLKIN cycles
60		10= 6 CPUCLKIN cycles

61		11= 7 CPUCLKIN cycles
62
63BIT=0           ; Reserved - write 0
64		0= unknown
65		1= unknown
66
67INDEX=15h       ; Block 2 RAM timing (Read/Write)
68BIT=76          ; DRAM wait states
69		00= 3 ws
70		01= 4 ws
71		10= 5 ws
72		11= Reserved
73
74BIT=5           ; Reserved - write 0
75		0= unknown
76		1= unknown
77
78BIT=43          ; -RAS <0:1> Precharge time
79		00= 4 CPUCLKIN cycles
80		01= 6 CPUCLKIN cycles
81		10= 8 CPUCLKIN cycles
82		11= 8 CPUCLKIN cycles
83
84BIT=21          ; -RAS <0:1> Refresh pulse width
85		00= 4 CPUCLKIN cycles
86		01= 5 CPUCLKIN cycles
87		10= 6 CPUCLKIN cycles
88		11= 7 CPUCLKIN cycles
89
90BIT=0           ; Reserved - write 0
91		0= unknown
92		1= unknown
93
94INDEX=17h       ; Block 3 RAM timing (Read/Write)
95BIT=76          ; DRAM wait states
96		00= 3 ws
97		01= 4 ws
98		10= 5 ws
99		11= Reserved
100
101BIT=5           ; Reserved - write 0
102		0= unknown
103		1= unknown
104
105BIT=43          ; -RAS <0:1> Precharge time
106		00= 4 CPUCLKIN cycles
107		01= 6 CPUCLKIN cycles
108		10= 8 CPUCLKIN cycles
109		11= 8 CPUCLKIN cycles
110
111BIT=21          ; -RAS <0:1> Refresh pulse width
112		00= 4 CPUCLKIN cycles
113		01= 5 CPUCLKIN cycles
114		10= 6 CPUCLKIN cycles
115		11= 7 CPUCLKIN cycles
116
117BIT=0           ; Reserved - write 0
118		0= unknown
119		1= unknown

Upon entering CTCHIP34, I see that:

DRAM Wait States = 5 ws
That is, index 11h, 13h, 15h, and 17h, Bits 7:6, are 10, meaning 5 ws.

RAS precharge time says (bits 4:3) = 4 CPUCLKIN cycles (00), which is in contrast to the BIOS, which states 3 CPUCLKIN cycles. However, the databook doesn't list 3 as an option, only 4, 6, 8, and 8 again.

RAS Refresh pulse width (bits 2:1) = 6 CPUCLKIN cycles (10), which is my correct BIOS setting.

When I try to adjust the the DRAM wait states for all four memory blocks to 4 ws (01), the DRAM wait states gets adjusted to 3 ws (00), and the RAS pulse width shifts from 6 CPUCLKIN cycles to 4 CPUCLKIN cycles. I exit CTCHIP34 and re-enter CTCHIP34 to confirm that DRAM wait states is still at 3 ws, it is. Next, I ran cachechk and DOOM, but the results did not improve at all.

Did you try using CTCHIP to adjust any of the other chipset registers which are known to actually have an affect when adjusted in the BIOS?

CAS Pulse Width is the setting that affects DRAM Read Speed. Can the lowest setting be used with the lowest Wait State?

It looks like 18-19FPS is about the score to get anyway, which it already gets. The symphony board has pipelined read access(?) so is hard to beat.