arti9m wrote on 2024-11-16, 21:24:

Coming soon, will be open source. Will work with Dual Slot-1 440BX boards.

You're the best! I look forward to it.

arti9m wrote on 2024-11-16, 21:24:

Coming soon, will be open source. Will work with Dual Slot-1 440BX boards.

I knew something triggered my ppro-sense.

arti9m wrote on 2024-11-16, 21:24:

Coming soon, will be open source. Will work with Dual Slot-1 440BX boards.

king shit!

arti9m wrote on 2024-11-16, 21:24:

Coming soon, will be open source. Will work with Dual Slot-1 440BX boards.

That is ... erhm, what do you say ... AWESOME!

Could be really cool to try a pair in say, my P2B-DS 😎 may need some messing around for bios support, though ..

I currently have a period-made slocket 8 running a 512KB PPro200 @ 2x124MHz in my P3B-F. So if you get lucky with the silicon lottery I would believe 2x133 could be achievable.

Can I have some more info on the AM2 compatible coolers ? I need to upgrade my original coolers to my micronics w6+li.Can you give me some pictures or better the model and the maker of the heatsink?
Edit. I just saw that you use the back plate of an AM2 cpu heatsink so it won't work on a ppro motherboard.What about dual 440fx motherboards ? Can I use your adaptors to my Siemens nixford d992 dual slot 1 motherboards ?

H3nrik V! wrote on 2024-11-17, 13:13:

Could be really cool to try a pair in say, my P2B-DS 😎 may need some messing around for bios support, though ..

It will work on P2B-D(S), already tested during development.
I'll share the working BIOS for that board and a few others (or sir @kmeaw will, many thanks to him).

Just give me a week, busy with work and I still need to smoketest my adapters at higher FSBs.

Just so that knowledge doesn't vanish if I disappear, for 440BX the secret is to connect pin BR1 from Slot to BR3 of PPro (by default slot BR1 is connected to CPU BR1).
Pin BR0 should remain connected to BR0 of the CPU.
This all means that owners of existing adapters can cut some traces and apply some bodge wires. My adapter has a tiny jumper to select between BR1/BR3.

Also, beware of that Asus "TRUE RETRO" clone adapter... If you own one, tape three 3.3V pins or cut the traces before it fries your VRM.

amijim wrote on 2024-11-17, 16:42:

Can I have some more info on the AM2 compatible coolers ?

Only that Asus clone has holes for properly installing AM2 coolers (with backplates), but I personally couldn't make it work.
You will have to get creative with the coolers on other adapters. The biggest problem is finding the retention spring. Some cheap aftermarket AM2 coolers have a spring that can be bent to fit Socket 8.
Also some aftermarket Socket 478 coolers have two compatible brackets/springs on the sides.

Aside from that, it's becoming tricky to find a heatsink that is flat on the whole surface area. Most of what you find today is designed to make contact with small CPUs.
PPro has a giant heatspreader, and you really DO need to make contact to the whole surface.
Again, aftermarket 478 and stock AM2 heatsinks (and 754/939) would work.

I mean, if you use the 1mb chips, you can use any heatsink. ^.^

Hello again , do you think these heatsinks will work? So I need to use the original lever holder or the one that comes with the AM2?

amijim wrote on 2024-11-17, 22:22:

Hello again , do you think these heatsinks will work? So I need to use the original lever holder or the one that comes with the AM2?

1. You need to see if the bottom surface is big enough for Pentium Pro. On the photos you provided you can't see surface that will make contact with the CPU.
2. What kind of adapters do you have? If you want to install the cooler on the socket directly, there is currently no existing product that will "just work". You will have to bend the spring, and on your photos the sprint is pretty thick, so you'll either break it or will have to heat it up considerably before bending it.

I'm interested in this adapter, good work! I have some CPU server card that can donor Socket 8 ZIF and some LX/BX MBs to try 😀 Do all MB needs BIOS mod or some just work with stock BIOS or just microcode update?

I want one to test on my IBM GL Slot1 PentiumII Computer

RayeR wrote on 2024-11-26, 16:59:

Do all MB needs BIOS mod or some just work with stock BIOS or just microcode update?

Most motherboards need a BIOS update as the firmware expects to have at least a Pentium II and reads/writes MSRs that do not exist on PPro, which results in a #GP.
Also an SMM transition freezes the whole system - probably due to the differences in the save state area layout. A proper fix is pending but for now we can just avoid SMI.

1%macro orgpatch 2
2%push patch
3%assign patch_cursor %2
4%$patch_start:
5%endmacro
6
7%macro relpatch 2
8        %1 (%2 + %$patch_start - patch_cursor)
9%endmacro
10
11%macro endpatch 0
12        %pop
13%endmacro
14
15; awardext.rom
16; 0001779C  0F32              rdmsr
17; 0001779E  66A900008000      test eax,0x800000
18; 000177A4  7504              jnz 0x77aa
19; 000177A6  6661              popad
20; 000177A8  EB04              jmp short 0x77ae
21; 000177AA  6661              popad
22; 000177AC  B00F              mov al,0xf
23; 000177AE  8D...              lea si, ...
24orgpatch 0x1000, 0x779c
25        times 10 nop
26endpatch
27
28; original.tmp
29; E000:E4D0-E000:FFFF is unused (FF)
30orgpatch 0x5000, 0xe4d0
31        pushad
32        mov eax,1
33        cpuid
34        and ax,0xfff0
35        cmp ax,0x630
36        jnl not_ppro
37        popad
38        pop cx
39        pop ax
40        add cx,ax
41        jmp cx
42not_ppro:
43        popad
44        mov ecx,0x11e
45        rdmsr
46        ret 2
47endpatch
48
49orgpatch 0x5000, 0xe500
50        pushad
51        mov eax,1
52        cpuid
53        and ax,0xfff0
54        cmp ax,0x630
55        jl ppro
56        popad
57        mov al,0xa4 ; generate SMI on Intel chipsets
58        mov dx,0xb2
59        out dx,al
60ppro:

61        ret
62endpatch
63
64; 000E318D  66B91E010000      mov ecx,0x11e
65; 000E3193  0F32              rdmsr
66; 00E3195  662500008000      and eax,0x800000
67orgpatch 0x5000, 0x318d
68        push byte 0x17
69        mov si,0x8c8f
70        relpatch call, 0xe4d0
71endpatch
72
73; 000E38DF  66B91E010000      mov ecx,0x11e
74; 000E38E5  0F32              rdmsr
75; 000E38E7  66C1E814          shr eax,byte 0x14
76orgpatch 0x5000, 0x38df
77        xor eax, eax
78        push byte 0
79        relpatch call, 0xe4d0
80endpatch
81
82; 000E3A2D  0FA2              cpuid
83; 000E3A2F  83E0F0            and ax,byte -0x10
84; 000E3A32  A90010            test ax,0x1000
85; 000E3A35  0F85E601          jnz near 0x3c1f
86; 000E3A39  3D3006            cmp ax,0x630
87; 000E3A3C  0F8CDF01          jl near 0x3c1f
88; ...
89; 000E3C57  F8                clc
90; 000E3C58  EB01              jmp short 0x3c5b
91; 000E3C5A  F9                stc
92; 000E3C5B  1F                pop ds
93; 000E3C5C  6661              popad
94; 000E3C5E  C3                ret
95orgpatch 0x5000, 0x3a3c
96        relpatch jl near, 0x3c57
97endpatch
98
99; 000E8CFC  66B91E010000      mov ecx,0x11e
100; 000E8D02  0F32              rdmsr
101orgpatch 0x5000, 0x8cfc
102        push byte 0x16
103        relpatch call, 0xe4d0
104        times 3 nop
105endpatch
106
107; 000ED483  B0A4              mov al,0xa4
108; 000ED485  BAB200            mov dx,0xb2
109; 000ED488  EE                out dx,al
110orgpatch 0x5000, 0xd483
111        relpatch call, 0xe500
112        times 3 nop
113endpatch

Yes, it makes sense. Disabling RD/WRMSR by NOPs should be easy. SMM/SMI handler is sill magic black box for me. I have some old awd bios sources but didn't digged inside so deep. I'm curious when SMM was commonly used first time on desktop systems. I know it was introduced in 486 CPU but it seems most 486 don't use SMM, maybe only laptops (for some power management). I don't know how heavily it's used on Pentium/II, if disabling all PM functions would be enought. On newer systems it was more extensively used e.g. for USB legacy emulation, SATA/IDE legacy emulation, SB/VSA and so on...

arti9m wrote on 2024-11-16, 21:24:

Coming soon, will be open source. Will work with Dual Slot-1 440BX boards.

Re: The thing no one asked for: KICAD 440bx reference schematic

😉

How are you supporting 3.2v?

myne wrote on 2024-11-27, 00:46:

How are you supporting 3.2v?

Slot-1 CPU or an adapter routes certain slot pins to GROUND to request a certain voltage from the motherboard voltage regulator.
By design, any fully P2-compatible Slot-1 mobo is supposed to be able to supply 1.8V to 3.5V.
However, those late overclocking boards _might_ have a different VRM that might be unable to supply 3V. In that case, the Pentium Pro CPU won't work, and so won't early P2 Klamath CPUs.

---

Anyways there is a setback. In attempts to make the adapter look as sexy as possible I failed to actually make it work in a dual 440BX system. It starts, but the CPUs are unable to sync due to excessive trace lengths (most likely).
Single CPU mode works fine upto 83 MHz FSB. I did succeed at running one CPU at 100MHz but there was basically zero tolerance and I wouldn't consider it stable.

I think the manufacturer also failed to maintain a requested board impedance, or there was a misunderstanding during order process. I will try and use lower termination resistance and see if it helps, but probably it won't.
While I do have control over adapter impedance, the mobo impedance is out of my control and all I can do is try to do things as standard as possible.

Now I'm thinking about a second revision, which will have socket oriented vertically, be 8-layer, will have length-matched traces (like late P3 slot CPUs) and should be as overclocking-friendly as possible.
It will certainly look less sexy but will probably actually work, which is kinda more important-ish.

If anybody want current gerbers or SprintLayout sources (yes I did it in SprintLayout, won't repeat that mistake), let me know. Adapters are safe to use, they just don't perform too well.

Hi, how many layers current design has? I think that 4-6 should be enoug including gnd/pwr planes. What PCB manuf. did.you ordered from? I use JLCPCB for some prototypes at work with high speed designs and no problem. When selecting options there's a choice for controled impedance and there you can select one of cca 8 stackups that are suitable for high speed designs. I use one with prepreg 95um thick that let me route diff pairs with minimal traces distance and thickness, e.g. something like 5/5mil trace/spacing. Does your layout sw support some traces length calculation and automated matching via accordeon patterns?

arti9m wrote on 2024-12-10, 22:33:

Slot-1 CPU or an adapter routes certain slot pins to GROUND to request a certain voltage from the motherboard voltage regulator. […]
Show full quote

myne wrote on 2024-11-27, 00:46:

How are you supporting 3.2v?

Slot-1 CPU or an adapter routes certain slot pins to GROUND to request a certain voltage from the motherboard voltage regulator.
By design, any fully P2-compatible Slot-1 mobo is supposed to be able to supply 1.8V to 3.5V.
However, those late overclocking boards _might_ have a different VRM that might be unable to supply 3V. In that case, the Pentium Pro CPU won't work, and so won't early P2 Klamath CPUs.

---

Anyways there is a setback. In attempts to make the adapter look as sexy as possible I failed to actually make it work in a dual 440BX system. It starts, but the CPUs are unable to sync due to excessive trace lengths (most likely).
Single CPU mode works fine upto 83 MHz FSB. I did succeed at running one CPU at 100MHz but there was basically zero tolerance and I wouldn't consider it stable.

I think the manufacturer also failed to maintain a requested board impedance, or there was a misunderstanding during order process. I will try and use lower termination resistance and see if it helps, but probably it won't.
While I do have control over adapter impedance, the mobo impedance is out of my control and all I can do is try to do things as standard as possible.

Now I'm thinking about a second revision, which will have socket oriented vertically, be 8-layer, will have length-matched traces (like late P3 slot CPUs) and should be as overclocking-friendly as possible.
It will certainly look less sexy but will probably actually work, which is kinda more important-ish.

If anybody want current gerbers or SprintLayout sources (yes I did it in SprintLayout, won't repeat that mistake), let me know. Adapters are safe to use, they just don't perform too well.

Ah right. Early vrm. Intel vrm spec 8.0 Iirc.
8.1 and 8.2 dropped 3.5v.

You might be interested in the script I made to convert asc files to kicad.
Or the full p2 reference board schematic.

Are you using 56ohm 1% termination resistors on the ha bus?
That's what the p2 called for

RayeR wrote on 2024-12-11, 00:16:

Hi, how many layers current design has? I think that 4-6 should be enoug including gnd/pwr planes.

I did it with 4, but 4 is just barely enough and was a PITA to work with. I had to mix power/ground planes with signal traces. There's quite a bit of overlapping lines going from Slot-1 to Socket-8, a lot of bridging is necessary. I would not recommend attempting similar projects with 4 layers. Go for 6 or 8.

RayeR wrote on 2024-12-11, 00:16:

What PCB manuf. did.you ordered from? I use JLCPCB for some prototypes at work with high speed designs and no problem. When selecting options there's a choice for controled impedance and there you can select one of cca 8 stackups that are suitable for high speed designs. I use one with prepreg 95um thick that let me route diff pairs with minimal traces distance and thickness, e.g. something like 5/5mil trace/spacing. Does your layout sw support some traces length calculation and automated matching via accordeon patterns?

I had to use NextPCB. You can choose controlled impedance there but they do not offer a choice for the stack-up. Due to where I reside, many popular PCB manufacturers are unavailable to me.
Regarding impedance, with GTL bus it is required to keep board impedance in certain window. Ofcourse you can't have it too high, but in this case you also can't have it too low. With this project I went with common sense + NextPCB calculator. Used 8 mil trace/spacing and requested impedance matching, and asked in comments (while ordering) to keep the board within 45-65 Ohm (according to PPro spec). Me using 8 mil basically means manufacturer could shrink the traces to increase impedance, if needed (and I had pre-paid for any such corrections). Ofcourse they also could've used different prepreg thickness.

A slight issue here is I am not a PCB or electronics engineer, just a hobbyist. I do understand the basics of signal transmission but I do not know how to properly calculate the impedance for 4-layer board, especially when most but not all of the inner layers are GND & Power planes.

Thankfully, PPro doesn't have a single differential pair. But for higher clock speeds I believe it is necessary to length-match most bus signals, like it is done on the late Slot-1 P3 and some good Socket 370 adapters.

I'm going with Altium with the next revision. It should make the design process a bit more foolproof.

myne wrote on 2024-12-11, 01:13:

You might be interested in the script I made to convert asc files to kicad. Or the full p2 reference board schematic.

Are you using 56ohm 1% termination resistors on the ha bus? That's what the p2 called for

Yeah I went for 56 Ohm, but 5% in my case. I too referenced P2, but PPro adapters from ALR use 75 Ohm, and Asus uses 68 Ohm I believe.
The tricky part is ideally this impedance should match the board impedance. And the tricky-tricky part is there are different chipsets out there that are terminated differently. 440FX and 440LX chipsets have 'classic' outer termination (with resistors around the chip) while 440BX has internal termination, and I do not know how exactly it works. Is it fixed to some value? Is it slightly configurable?
And yes, full board schematics could be of help.

Also dual 440BX boards can work with 1 CPU without a terminator in the 2nd slot. Which makes sense for GTL bus.
But most dual 440LX refuse to start without a terminator in the intermediate slot, despite electrically it is allowed by the specs. Anyone knows why?