Figured it out!
Convert old ASUS ASC boardviews to KICAD PCB!

Looks great. To quote Bill Hader in Tropic Thunder: Smack it up, flip it, rub it down!

Cheers 😀
Opened the files?
Should do OK as a defacto footprint importer

Any idea what the nails are? I thought they might be traces, but maybe just drill holes?

Going to sleep now, will read the script tomorrow.

We are all waiting for suitable AI autorouter (I wonder if it really happen in this decade), go PCB go...

The big boys already do.
Nvidia said it helped their designs

And what SW they use? AFAIK AD didn't announced any thrilling change in AD25 to theirs 20-year old useless autorouter...
But I think that optimal routing of e.g. SMPS or RF voodoo would be still done better by a human.

Wouldn't any autorouter technically be considered "AI"?

I mean... It's just Djakarta's algorithm...

The same thing that powers every router and google maps.
You might know it as OSPF.

It probably exists already, but costs a lot.

I think there are 2 different problems. One is to route all nets to be connected and don't violate any rules - clearance or short circuits. And second is to route it optimal way to minimize high current loops, add copper polygons and other stuff that is usually a lot of manual time-consuming work. While both routings may work, the manually optimised is much better according to EMI radiation/susceptibility and stability. This is the art to do it right way so I'm curious if AI get to this level to replace humans with tens of years experience of designings such PCB layouts...

When it comes to EMI computers might do a lot better than humans. Most EEs dont ever run any simulations or play with probes, resigning to established "common knowledge" including stupid crap like star ground routing or split ground planes. Automated solution will iterate with FEM simulations until it gradient descends into something correct .. after consuming megawatts in the process.

Computers are definitely better than humans.
It's just expensive to buy those secret sauces

myne wrote on 2024-12-09, 08:55:

Any idea what the nails are? I thought they might be traces, but maybe just drill holes?

Afaik FABMASTER was not manufacturing machine but a Tester. Nails because those types of tester use bed of nails setup to probe multiple points at the same time.
https://www.ipc.org/system/files/technical_re … E7%26S13_02.pdf

Lol
Nice to know boards back then survived the Spanish inquisition

You've got my attention. Really!

My wish is a P3 (+) motherboard containing not only 2 but 4 slot1 sockets.
Something that's never existed. The Slot-1 FSB, that derives from PPro, can support a maximum of 4 'agents' due to the electrical bus load. But logically it can accomodate 16 cpus. There are Netserver Variants with 2 CPU cards containing 3 PentiumPros each, so it is possible!
I'm also in line with your idea of using VRM modules like the one from necroware. We'd need 4 of these too, makes it easier for testing/debugging/replacing etc as the total CPU power load can get significant.

And I also already checked the slot1 pinout and counted the reserved and unused pins. They should be enoguh to upgrade the slot1 to also support anything above P3, as these need 4 additional signals for the DINV[0:3] signal and for the quadpumped FSB clocking. When someone one day achieves to simulate a 440BX/GX+ chipset into a CPLD or FPGA it's possible to upgrade the slot-1 to support this.

And thats's what I like about slot1: the possibility to built slotkets for all kind of cpus:
It would then be possible to design slotket adapters for Pentium M or Atom or Core2Quad (the last FSB-based CPU).
Imagine 4 slotkets running a Core2Quad each, totalling to 16 cores and running Win11.

My prior thoughts about slot-1 upgrades:
Introduction and CPU Adapter Idea
New Crazy Idea: Build a slot1 pcb for 2 cpus

Being opensource it would permit to design new motherboards in all kinds of formfactor. My utimate dream would be to upgrade my beloved old blueish Gericom 340s8 Webgine laptop from 2003 with a new fitting motherboard that can run Win11. Until then I need to redesign the case for 3D-printing, as the plastic begins to fall apart.

I 'm so crazy for the open-source retro movement, for the fun and ability to learn how it works!

I'll defenitely keep an eye on this thread!

Fun idea, but slot 1 is a subset of the PPro bus.
It lacks br1, and br2 for starters meaning the CPUs will clash. 4 simply won't work. Look up the slot2 xeon datasheets. They did 4 from memory.

The dual Slotket has some merit, but it also needs an ioapic and probably br3 wired somehow directly from the chipset.

myne wrote on 2024-11-23, 17:59:

Side note, the Pentium M seems to be GTL+ too. Wonder if it had latent bus backwards compatibility no one ever discovered... That'd be icing on the cake.

If someone happens to own a working pentium-M motherboard, he could try to short one or all of the DINV[0:3] signals (they're open-drain) and look if it still runs.

The DINV-signals >might< get output onto the bus first, derived from the parity signals, before they're probed for the bus transmitter to see if the signals should be inverted.

If YES: it is backward-compatible!

But I fear not as their logic is inverted and would need to be forced up!

The other thing are the quad-clock singals, that maybe can be supllied from the base FSb-clock, forcing the bus running at 1/4 aka base clock like the rest!

myne wrote on 2025-01-20, 12:30:

Fun idea, but slot 1 is a subset of the PPro bus.
It lacks br1, and br2 for starters meaning the CPUs will clash. 4 simply won't work. Look up the slot2 xeon datasheets. They did 4 from memory.

The dual Slotket has some merit, but it also needs an ioapic and probably br3 wired somehow directly from the chipset.

My question is: how can a netserver manage 6 cpus when there are only 4 BR pins? obviously there is some arbitration circuit inside the chipsets. The limit of 4 is due to the electrical limit, but not logically.

I thought about this (the last years to be exact!): Maybe it's possible to design a small arbitration circuit: either the CPU is active (BRP0) or not (BRP1:3). Does it matter for the CPU to know which of the BR pins is blocking it from accessing the bus currently? All that it needs to know is: I must wait (BRP1)

https://www.cpushack.com/2019/01/18/part-4-mi … d-overclocking/

This one?
Special chipset logic, apparently

A bit missing point of running W11 on such old HW. One may pick up some old multiprocessor server board from scrap and run W11 there. Probably even there'se some limitation that W11 requires some adv.Instruction set like SSEx so no way on Ppro/PII/PIII etc.