j^aws, these (s)s.7 motherboards with "turbo" switch functionality are not so common. I see that for some of your test results table you've manually disabled L1, L2 and L3 caches and switched to "de-turbo" mode for even slower CPU speed. Does this mean that the "turbo" switch in "de-turbo" mode reduces the FSB frequency even more as in cacheless 386 boards?

j^aws wrote on 2024-12-10, 18:05:

Disruptor wrote on 2024-12-10, 14:37:

Impressive chart.

Yes but SpeedSys shows now 9.26 and not the 0.45 from above. Has this low value not been reproduceable?

Yes, it's reproducible - the test just takes a very long time to complete. The 0.45 Speedsys is with all caches disabled (L1, L2 and L3), so there isn't a cache graph from Speedsys...

No, I just was interested where the 3 lines have been. I admitted they are straight horizontally, of course.

analog_programmer wrote on 2024-12-10, 22:11:

j^aws, these (s)s.7 motherboards with "turbo" switch functionality are not so common. I see that for some of your test results table you've manually disabled L1, L2 and L3 caches and switched to "de-turbo" mode for even slower CPU speed. Does this mean that the "turbo" switch in "de-turbo" mode reduces the FSB frequency even more as in cacheless 386 boards?

Yes, the idea was to treat it like an old 386 board with no off-die cache for some baselines, and use "de-turbo" to see the lower speeds. Not exactly sure on the mechanism used to attain the slow speeds as the reported clocks vary depending on the benchmark used. Speedsys is reporting TSC register to be unchanged (e.g. 100MHz posted for both Turbo and De-Turbo), whilst others report 9-10 MHz. They also give equivalents, e.g. Landmark says 2MHz AT (approximately 4MHz XT).

Board chipset is an SiS 5582 and presumably it's using something funky here with the clocking where 9-10 MHz maybe some fractional multiple of the Reference clock.

Disruptor wrote on 2024-12-11, 00:10:

j^aws wrote on 2024-12-10, 18:05:

Disruptor wrote on 2024-12-10, 14:37:

Impressive chart.

Yes but SpeedSys shows now 9.26 and not the 0.45 from above. Has this low value not been reproduceable?

Yes, it's reproducible - the test just takes a very long time to complete. The 0.45 Speedsys is with all caches disabled (L1, L2 and L3), so there isn't a cache graph from Speedsys...

No, I just was interested where the 3 lines have been. I admitted they are straight horizontally, of course.

Okay, I see. It's still interesting to see cache breakdowns where applicable.

j^aws wrote on 2024-12-11, 00:23:

Okay, I see. It's still interesting to see cache breakdowns where applicable.

Thanks. You perhaps are able to save the chart with SpeedSys' save function. It will generate a .pcx file which can be converted to .png and a .txt file too where I can see the abysmal performance in detail then 😀

Disruptor wrote on 2024-12-11, 02:25:

j^aws wrote on 2024-12-11, 00:23:

Okay, I see. It's still interesting to see cache breakdowns where applicable.

Thanks. You perhaps are able to save the chart with SpeedSys' save function. It will generate a .pcx file which can be converted to .png and a .txt file too where I can see the abysmal performance in detail then 😀

Sure! Can save extra details in this format. Hardware is in storage currently, so will look at this when I get back to testing in the future.

j^aws wrote on 2024-12-11, 00:23:

Yes, the idea was to treat it like an old 386 board with no off-die cache for some baselines, and use "de-turbo" to see the lower speeds. Not exactly sure on the mechanism used to attain the slow speeds as the reported clocks vary depending on the benchmark used. Speedsys is reporting TSC register to be unchanged (e.g. 100MHz posted for both Turbo and De-Turbo), whilst others report 9-10 MHz. They also give equivalents, e.g. Landmark says 2MHz AT (approximately 4MHz XT).

Board chipset is an SiS 5582 and presumably it's using something funky here with the clocking where 9-10 MHz maybe some fractional multiple of the Reference clock.

I see. I have a s.7 mobo (Elpina M571 v.3.2A) with very similar highly integrated (for its time) SiS 5598 chipset. It seems like SiS 5598 chipset is just a variant of SiS 5582 with IGP. The board has undocumented "turbo" switch pins on the front panel connector, but I've never tried if it works in "de-turbo" mode. I read some forum posts that "de-turbo" switch connected to those two pins doesn't work at all. But there's also some undocumented jumper setting for "REF" FSB setting, and this "REF" setting for the CPU and RAM frequency is equal to 14.31818 / 2 = 7,15909 MHz (half the FSB crystal oscillator value). Maybe I should try it.

That turbo pin on 586 mobos is usually for the turbo light (not actual turbo fubction, which 586 mobos basically never have) but maybe this thread is the one that uncovers the exceptions?

Some users have reported soft switching still active on some pentium boards with ctrl-alt-+ or - on the numpad.

BitWrangler wrote on 2024-12-19, 23:40:

Some users have reported soft switching still active on some pentium boards with ctrl-alt-+ or - on the numpad.

Oh, interesting….

Sphere478 wrote on 2024-12-19, 22:13:

That turbo pin on 586 mobos is usually for the turbo light (not actual turbo fubction, which 586 mobos basically never have) but maybe this thread is the one that uncovers the exceptions?

Some Socket 7 motherboards from Gigabyte has a working pin for the Turbo switch, but it will only toggle 50 MHz FSB.