myne wrote on 2024-12-21, 14:45:

Which pin on the slot?
If it's B21, it's the dual processor pin.

I'm pretty sure B21 on most boards is interpreted as BSEL0, used to set board FSB frequency CPUs to 66/100 MHz.
On PPro and P2 it is tied to GND.

I am talking about B12, which is unused on P2/P3, but on Asus C-P6S1 it is tied to Socket 8 pin AG3, which is an "Upgrade Present" pin used only by P2 Overdrive.

RayeR wrote on 2024-12-22, 00:09:

BTW when talking about stubs on the SMP FSB... I remeber that I saw some dummy CPU boards (not sure if slot1 or PGA370) that was intended to be inserted in an empty CPU socket of dual CPU MB (if only one CPU used), probably containing some terminating resistors that lowered reflections from the unconnected bus stub ends.

Yeah, many boards actually require a terminator in the intermediate slot and won't even start without it. But Asus P2B-D(S) works just fine without it.

RayeR wrote on 2024-12-22, 00:09:

just think it would be a bit fun to push PPro harder in MB that allows higher FSB...

83 MHz is the max with my boards, no way to push it further. Most 512K and 1M CPUs won't go to 100MHz anyway tho.

The one 512kb part I tried in my period slocket went up to 124MHz x2 just fine, but maybe I just got lucky

maxtherabbit wrote on 2024-12-22, 01:20:

The one 512kb part I tried in my period slocket went up to 124MHz x2 just fine, but maybe I just got lucky

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Extremely. With a proper slocket adapter I can't reach 100 with both of my 512K CPUs. Won't post no matter what. Not a single post code.
My 256K goes to about 115.

Yeah the traces are too far away from the same length. It's actually kinda surprising it works at 66

If anyone wants to play route the wire
Done the basic schematic, and rough layout in kicad.

It's very rough so don't expect it to be correct

myne wrote on 2024-12-22, 08:13:

Yeah the traces are too far away from the same length. It's actually kinda surprising it works at 66

Nah, there was never a hard requirement for the signals to arrive at the same time for 66 (with PPro at least). 66 works fine with a lot of bodge wires while 100 doesn't even try to POST.
Take a look at some native PPro boards - not only the traces are of various length, but the termination resistors are all over the place. Some are placed before the traces reach the CPU.
What's really surprising to me is how much more sensetive 100MHz to the routing is compared to 66. It really was a huge milestone back then.

It's all about the timing of the signal arriving before the "photo finish".
64 horses in a race and they've all got to do a lap and get within the same photo frame at the finish line in 10nanoseconds.
Miss the clock, it all falls over.

13ns is a donkey race.

myne wrote on 2024-12-22, 15:50:

It's all about the timing of the signal arriving before the "photo finish".
64 horses in a race and they've all got to do a lap and get within the same photo frame at the finish line in 10nanoseconds.
Miss the clock, it all falls over.

If it was the case, Intel would've just make the traces as short as possible in P2/P3. However you can see that they actually went for length-matched traces, not as short as possible. Something to do with noise, perhaps?
I've also been told before that if you cut the trace in P3-to-Slot1 adapter and bodgewire it while making it shorter, the adapter fails to work at higher frequencies, but if you respect the original length, it will work just fine.

I think you misunderstood my bad analogy.

They all have to get to the finish and fit in the same photo. The photo is a metaphor for the clock that measures the bits(horses) at that moment.

So they all have to be the same speed and run the same distance. It's still important at 66,but the tolerance is 30% higher.

A donkey race is a LOT less memorable than a donkey SHOW.

I'll never forget that week I spent in Tijuana when I was 21...

luckybob wrote on 2024-12-23, 14:48:

A donkey race is a LOT less memorable than a donkey SHOW.

I'll never forget that week I spent in Tijuana when I was 21...

Barranquilla!

Still learning kicad.
All memory bus length matched to 46mm.
Had to use traces on 4 layers, and I know there are issues there but...
Comments anyone?

While being so awful as mr Artyomka says, the C-P6S1 clone of mine easily holds 124 MHz in dual config . At least a dual S1 VIA mobo did that. I will make a revision using our good old local Mikrolit fab and test it in dual BX system in a month with a jumper suggested by my Belorussian copycat and a hater junior colleague Artyom. I will report here if the frequency issues were caused by unmatched lengths of conductors. But , I used to overclock tualatins up to 152 MHz using $3 slotkets for Mendocino with no signs of length-matched conductors. As for shortening cache power line in my copy of Asus - well, shit happens. However, this helped me running a capable PPro @ 2x133 @ 3.8v in some badly-designed mobo for a while. No VRM and/or CPU was burned so far and I’ve sold almost a hundred of those unsexy slotkets. I’m not planning to export them anymore. I think open source version , created by a community will be better anyway.

The BIOSes of Slot2 mobos still have code that prints “Pentium Pro” when could not properly detect a CPU.

Mentat, I wouldn't take the negatives too seriously, your design have proven itself and that is what counts.

As for slockets, same here, done numerous mods to cheapest slockets in order to run Tualatins and proper pin isolation and vtt connections were what mattered. My gaming rig in 2003 or so was Gigabyte GA-6ZMA with some 370CPU card modified for 1300 Celeron running at 1733 MHz @ 1.65 volts (b-stepping, took trying several chips to succeed), 512MB RAM, Geforce 3 Ti500.

Can't wait for 133 MHz capable slocket-8's, would love to try them on BX boards.
Good luck!

P.S. Is that Compaq SP750 on your photo with dual Xeon 900's?

Paadam wrote on 2024-12-30, 22:14:

P.S. Is that Compaq SP750 on your photo with dual Xeon 900's?

Thanks for support. “My design” actually works because it’s Asus design )
And yes it’s the Compaq, my second Slot2 rig with a couple of Cascades 900/2M (5/12v this time) with some ECC RDRAM and V56k clone from Anthony zxc64. There’s a trouble detecting of proper frequency from the BIOS , but cache is active.
Maybe I’ll dig into Intel BIOS some day to fix cache init in some other cool mobos. There are plenty of Intel SLOT2 boards with SOIC ICs, but I found one with a place for optional PLCC Bios IC where one could install a socket.

Mentat-vvo wrote on 2024-12-29, 12:29:

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The BIOSes of Slot2 mobos still have code that prints “Pentium Pro” when could not properly detect a CPU.

There's a LOT of money in that image. And still, the hard drive is just hanging like that is just such an juxtaposition.

if you decide to let that overdrive go, my ALR needs a few more to complete the set...

I probably should have looked earlier, but it seems that when it comes to Intel's recommendations on trace spacing, board makers don't pay any attention.
I was wondering how all the slotkets looked so neat, and how motheboards managed to route all the wires. I looked at https://theretroweb.com/motherboards/s/asus-cubx-l
And it's obvious that literally zero traces have the recommended 12mil spacing. If they're 5mil traces, they look like 2mil spacing.
Yet it all apparently works.

Oh well, here's the progress so far.

The needed spacing very depends how far is the ground plane from signal traces. If you have a thin prepreg and gnd plane just below you need much less spacing than in case of simple 2 layer PCB where the gnd plane distance is thickness of fr4 core. It may be e.g. 0.1 vs 1.6mm, thats huge difference...

Why is that not mentioned anywhere?!