dear friend, I have many 16MB 72-simm with 16chips, does anyone have idea to make an address decode circuit to judging A10 when /RAS=0, if A10=1 enable high part of 16MB memory, if A10=0 enable low part of 16MB memory?
is it possible serial two 16MB memory and design an raw address decoding circuit to control two part of 16MB?
thanks though it is not what I mean. now we parallel chips(using 4MB*4 chips parallel to 32MB*8 simm),can we using 2MB*4 parallel to two 16MB*8 part, and adding address decode circuit to output each part ?
thanks though it is not what I mean. now we parallel chips(using 4MB*4 chips parallel to 32MB*8 simm),can we using 2MB*4 parallel to two 16MB*8 part, and adding address decode circuit to output each part ?
thanks though it is not what I mean. now we parallel chips(using 4MB*4 chips parallel to 32MB*8 simm),can we using 2MB*4 parallel to two 16MB*8 part, and adding address decode circuit to output each part ?
dear friend, I have many 16MB 72-simm with 16chips, does anyone have idea to make an address decode circuit to judging A10 when /RAS=0, if A10=1 enable high part of 16MB memory, if A10=0 enable low part of 16MB memory?
is it possible serial two 16MB memory and design an raw address decoding circuit to control two part of 16MB?
Classic boards expect the memory chips to have a square layout. 32MB PS/2 SIMMs are supposed to have two "ranks" of 16M each, each of which is built as 4M x 32. This means your 16-chip modules are built from 4M x 4 chips, 8 of them yielding one "rank". You ask about building them from 2M * 4 chips. Do they actually exist? I can find 2M * 4 * 2 banks SDRAM chips, but I don't seem to find 2M * 4 EDO or FPM chips at all.
But let's suppose that they exist. These chips are likely to have an 11/10 adressing scheme (11 row bits, 10 column bits) or a 10/11 addressing scheme. As you write your question, you seem to talk about (hypothetical) chips that use a 10/11 scheme, so they don't use A10 while /RAS=0. You want to build a DRAM that contains 32MB, which is typically 2 ranks with 11 row bits and 11 column bits. Generally, this is possible. You "just" need some intermediate chip that latches A10 on the falling edge of /RAS and uses that to multiplex what set of 10/11-adressed 2M*4 chips the /RAS signal will be forwarded to. This would mean delaying /RAS to the selected chips, which is bad. Better, you multiplex the two sets of chips via /CAS. If /RAS is low, forward /CAS only to the bank selected by A10 during the falling edge of /RAS. If /RAS is high, forward /CAS to both sets of chips (for /CAS-before-/RAS refresh to work). Delaying /CAS is not as bad as delaying /RAS, as delaying /RAS may cause the row address to be no longer present on the address lines whan /RAS is lowered. On the other hand, I expect a hold time (even if not required) after /CAS to be sufficient for /CAS to be demultiplexable.
Damn. You know a lot about ram addressing.
Got a question for someone with your knowledge.
The 440bx can address 1gb, and the 40gx can address 2gb of ram.
Possibly due to chip size limitations at the time, these both used 4 slots to do so.
I'm wondering if it is possible to rearrange the lines so it can be done in 2 slots.
See Pg 13-16 of below. Bx doesn't have maa14, mab14 but is otherwise the same.
The 440bx can address 1gb, and the 40gx can address 2gb of ram.
Possibly due to chip size limitations at the time, these both used 4 slots to do so.
I'm wondering if it is possible to rearrange the lines so it can be done in 2 slots.
I am looking at the GX chipset here: https://www.datasheetcatalog.com/datasheets_p … 4/82443GX.shtml . Look at table 4-10 on PDF page 98 (document page 4-18). it indicates how FSB address bits are routed to the MA lines. The biggest RAM option is 512 megabytes per "rank". The chipset datasheet assumes this option can only be obtained using 16 chips each organized as 64M x 4 (a kind of 256 MBit chips). As the chipset is not strong enough to drive 16 chips per module, the datasheet asks for registered DIMMs in that case. As we now have 512 MBit chips, e.g. the MT48LC64M8A2 organized as 64M x 8, you can now produce 512MB per rank using only 8 chips, which can be driven by the 440GX on non-registered SIMMs. I checked the datasheet, and the addressing scheme of that new 512MBit chips seems to be identical to the address scheme of the 256MBit chips that should be supported according to the data sheet. This means a DIMM which has two ranks (commonly called "sides"), each rank having 8 chips organized as 64M x 8, has 1GB, and two of those DIMMs will provide 2GB RAM. You don't need to re-wire any adressing bits, this scheme seems to be supported out-of-the-box.
On the other hand, the 440BX only supports addressing up to 128MB per rank, topping out at 1GB if 8 ranks (4 slots) are installed. Multiplexing two slots to one slot with SDRAM is likely not possible, as the Intel chipset can open different rows in each rank at the same time. All but the smallest SDRAM chips allow 4 open rows (one in each bank) at the same time, so if you map 2 slots to one slot, the chipset expects to be able to open 4 rows on the first rank of the first slot, 4 rows on the second rank of the first slot, 4 rows on the first rank of the second slot and 4 rows on the second rank on the second slot, i.e. 16 rows in total. A bigger module inserted into a physical slot that should appear as two modules to the 440BX only has 4 banks on the first rank ("front side") and 4 banks on the second rank ("back side"), so it can open only 8 rows at the same time.
You might have to dumb the rest down a bit.
I understand that 1 slot= 2 ranks.
I get that each rank is 8 chips.
I vaguely get the internal chip arrangement.
I don't really understand why 13 address lines can't achieve in one slot what it does in 2.
No, not generally. One rank is 64 bits (or 72 bits with ECC). Depending on the chip type, this is 16 chips providing 4 bits each (called "x4" chips), 8 chips providing 8 bits each or 4 chips providing 16 bits each. Theoretically you could also have 2 chips providing 16 bits each, but I don't think such SDRAM chips ever got common. Due to the limited drive strength of the 440 north bridges, it is forbidden to connect 16 chips to one rank, so if you want to use x4 chips, you need an amplifier inbetween, as you get on registered DIMMs.
I don't really understand why 13 address lines can't achieve in one slot what it does in 2.
I guess this is easy to explain: 13 address lines as used by the 440BX can only address 128MB. The 440BX individually selects one of the 8 ranks (2 per slot). So every slot can only supply 2 ranks of 128MB. Notwithstanding the issue of open rows: If you want to put 512MB into one slot, you need to combine rank select lines, to make 2 rank select lines out of 4 rank select lines, and you need to supply the information which rank was originally selected as extra address bit. This involves not only wiring, but also some logic, which will obviously delay the rank select signal.
To get me on track on what's in your mind: Do you think about dealing with bigger ranks (bigger chips), or do you think about providing four instead of two ranks in one slot (more chips)?
dear friend, I have many 16MB 72-simm with 16chips, does anyone have idea to make an address decode circuit to judging A10 when /RAS=0, if A10=1 enable high part of 16MB memory, if A10=0 enable low part of 16MB memory?
is it possible serial two 16MB memory and design an raw address decoding circuit to control two part of 16MB?
Classic boards expect the memory chips to have a square layout. 32MB PS/2 SIMMs are supposed to have two "ranks" of 16M each, each of which is built as 4M x 32. This means your 16-chip modules are built from 4M x 4 chips, 8 of them yielding one "rank". You ask about building them from 2M * 4 chips. Do they actually exist? I can find 2M * 4 * 2 banks SDRAM chips, but I don't seem to find 2M * 4 EDO or FPM chips at all.
But let's suppose that they exist. These chips are likely to have an 11/10 adressing scheme (11 row bits, 10 column bits) or a 10/11 addressing scheme. As you write your question, you seem to talk about (hypothetical) chips that use a 10/11 scheme, so they don't use A10 while /RAS=0. You want to build a DRAM that contains 32MB, which is typically 2 ranks with 11 row bits and 11 column bits. Generally, this is possible. You "just" need some intermediate chip that latches A10 on the falling edge of /RAS and uses that to multiplex what set of 10/11-adressed 2M*4 chips the /RAS signal will be forwarded to. This would mean delaying /RAS to the selected chips, which is bad. Better, you multiplex the two sets of chips via /CAS. If /RAS is low, forward /CAS only to the bank selected by A10 during the falling edge of /RAS. If /RAS is high, forward /CAS to both sets of chips (for /CAS-before-/RAS refresh to work). Delaying /CAS is not as bad as delaying /RAS, as delaying /RAS may cause the row address to be no longer present on the address lines whan /RAS is lowered. On the other hand, I expect a hold time (even if not required) after /CAS to be sufficient for /CAS to be demultiplexable.
sorry 1M*4 per chip. hm514400, that is seems a0-a9，how can I deal with a10? /ras=0 latched, /cas=0 latched, and using two latched A10(r) A10(c) control /we /oe?
by the way if i using 51v17400 3.3v chip, is the signal line need a 3.3v protect zena diode? because the input signal maybe 5v in 486 board.
sorry 1M*4 per chip. hm514400, that is seems a0-a9，how can I deal with a10? /ras=0 latched, /cas=0 latched, and using two latched A10(r) A10(c) control /we /oe?
by the way if i using 51v17400 3.3v chip, is the signal line need a 3.3v protect zena diode? because the input signal maybe 5v in 486 board.
Be aware that building a 32MB SIMM (no parity) from 1M*4 chips requires 64 chips. That's a lot of chips, and you might need to buffer the control lines if you want to use multiple of those SIMMs at the same time. If you buffer the address lines, I recommend to buffer /RAS and /CAS as well, to keep the timing relationship between the address lines the same.
You should latch A10 at the edge of /RAS assertion (latching it at the /RAS edge should work as well as latching it while /RAS is low). A10 during /CAS assertion is likely to stay constant throughout the cycle, so it is likely you get away to decode A10(r) and live A10 to select a "subbank". You can select the subbank by dispatching /OE and /WE, but the "classic" approach is to dispatch /CAS instead. For PS/2 SIMMs, decoding /OE and /WE seems like the easier approach, as there is only a single /WE and no /OE at all on the host side. Furthermore, leaving /CAS untouched also enables /CAS-before-/RAS refresh, which would need special treatment if you dispatch /CAS to the "selected" subbank only.
The logic to latch A10 while /RAS is asserted, and generating /WEx and /OEx per subbank should fit into a single PAL, somehow like this (sorry, I'm not fluent in PAL assembly syntax, so I likely get details wrong):
mkarcherwrote on 2025-01-14, 07:52:Be aware that building a 32MB SIMM (no parity) from 1M*4 chips requires 64 chips. That's a lot of chips, and you might need to b […] Show full quote
sorry 1M*4 per chip. hm514400, that is seems a0-a9，how can I deal with a10? /ras=0 latched, /cas=0 latched, and using two latched A10(r) A10(c) control /we /oe?
by the way if i using 51v17400 3.3v chip, is the signal line need a 3.3v protect zena diode? because the input signal maybe 5v in 486 board.
Be aware that building a 32MB SIMM (no parity) from 1M*4 chips requires 64 chips. That's a lot of chips, and you might need to buffer the control lines if you want to use multiple of those SIMMs at the same time. If you buffer the address lines, I recommend to buffer /RAS and /CAS as well, to keep the timing relationship between the address lines the same.
You should latch A10 at the edge of /RAS assertion (latching it at the /RAS edge should work as well as latching it while /RAS is low). A10 during /CAS assertion is likely to stay constant throughout the cycle, so it is likely you get away to decode A10(r) and live A10 to select a "subbank". You can select the subbank by dispatching /OE and /WE, but the "classic" approach is to dispatch /CAS instead. For PS/2 SIMMs, decoding /OE and /WE seems like the easier approach, as there is only a single /WE and no /OE at all on the host side. Furthermore, leaving /CAS untouched also enables /CAS-before-/RAS refresh, which would need special treatment if you dispatch /CAS to the "selected" subbank only.
The logic to latch A10 while /RAS is asserted, and generating /WEx and /OEx per subbank should fit into a single PAL, somehow like this (sorry, I'm not fluent in PAL assembly syntax, so I likely get details wrong):
/A10R is the latched version of A10 (inverted, because PALs like that), which will be routed to an output pin that's not connected on the PCB.
thanks very much. I have learnt how to "serial extend", word extend in digital logic circuit, your explanation is very detail, which is the best relay for my question. ＂serial extend ＂is trouble me for a long time, I will learn it carefully,to understand the dram.
the second question, if i use 51v17400-50 3.3v chip, is the signal line using 74f
244 245 buffer? because the input signal maybe 5v in 486 board. and which signal can be use as data-line-in-out-direction control? otherwise I will choose auto direction voltage shifter.
a third question, -50 chips is good for old board which commonly paired with -60 memory.
I'm sorry, I don't fully understand your question. On a 486 board, you should expect 5V levels on the memory data and address lines. This is true if the RAM is directly connected to the chipset. This is also true if the RAM is connected via a 74f244 or 74f245 buffer. You might get away with current limiting resistors on the data lines and rely on the protective diodes in the chip, or you might get away with overvolting the chip to 4.5V, but both is out of spec and can damage the chip. Using level shifting or level clamping buffers is the best thing to do.
If you want to add a (level shifting) buffer, there is no one signal you can use for direction control. You may only drive data from the RAM to the board if your SIMM slot is active (on of the /RAS lines low, also/CAS low, more difficult with EDO) and /WE negated (high). In all other cases, it is OK to drive data from the board to the chip. You can use /WE as direction control, but you would need to generate /OE for that chip as OE = /RAS0*/CAS + /RAS1*/CAS + /RAS2*/CAS + /RAS3*/CAS.
Thinking about it again, I think I should not have written the slash in front of the output signals in the PAL equations in my last post. That will probably yield the negated result of what I meant.
50ns chips are likely fast enough if you stay at 33MHz FSB.
mkarcherwrote on 2025-01-15, 21:49:I'm sorry, I don't fully understand your question. On a 486 board, you should expect 5V levels on the memory data and address li […] Show full quote
I'm sorry, I don't fully understand your question. On a 486 board, you should expect 5V levels on the memory data and address lines. This is true if the RAM is directly connected to the chipset. This is also true if the RAM is connected via a 74f244 or 74f245 buffer. You might get away with current limiting resistors on the data lines and rely on the protective diodes in the chip, or you might get away with overvolting the chip to 4.5V, but both is out of spec and can damage the chip. Using level shifting or level clamping buffers is the best thing to do.
If you want to add a (level shifting) buffer, there is no one signal you can use for direction control. You may only drive data from the RAM to the board if your SIMM slot is active (on of the /RAS lines low, also/CAS low, more difficult with EDO) and /WE negated (high). In all other cases, it is OK to drive data from the board to the chip. You can use /WE as direction control, but you would need to generate /OE for that chip as OE = /RAS0*/CAS + /RAS1*/CAS + /RAS2*/CAS + /RAS3*/CAS.
Thinking about it again, I think I should not have written the slash in front of the output signals in the PAL equations in my last post. That will probably yield the negated result of what I meant.
50ns chips are likely fast enough if you stay at 33MHz FSB.
this is another new question , i get some 51v17400-50 3.3v chip,so i meet the 3.3v 5v level shifter problems, and thanks for your patience. I choose txb0108/txs0108 auto direction shifter. this is also the problem if i am design 64M simm by 3.3v chips
this is another new question , i get some 51v17400-50 3.3v chip,so i meet the 3.3v 5v level shifter problems, and thanks for your patience. I choose txb0108/txs0108 auto direction shifter. this is also the problem if i am design 64M simm by 3.3v chips
Also have a look at this application note by Pericom (acquired by Diodes Inc) on "zero delay bus switches", especially chapter 4 ("Conversion Between 5V and 3V Logic"). I've seen Pericom bus switches in that configuration (IIRC also some clones) on modern PCI graphics cards, in which the graphics chip is not 5V tolerant. I don't remember whether it's Pericom or a different manufacturer, but I do remember some vendor integrated the 5V-to-4.2V dropper diode into the bus switch, so you could just power it with 5V at get clamping to a level that's OK with 3.3V logic.
