I have finished my Octek Hippo 10 mod, see pictures. Had to do a little rewiring work on the back but it works fine otherwise. I'm looking forward to benchmarking it and see if it handles 40 MHz FSB properly.
do you have the pin out difinition of the 8498 8496?
Unfortunately not. I had to reverse engineer it.
rasz_pl wrote on 2024-03-25, 06:40:I still dont understand the need for any bios mods to enable PS2. Some bioses expect exact keyboard controller model/firmware version, but afaik there is nothing special about ps2 ports.
Sorry for the late reply: The PS/2 mouse interface is specified to work with BIOS assistance. The mouse driver is not supposed to directly interface with the keyboard controller, but the mouse driver will ask the BIOS to activate the PS/2 port and register a callback function with the BIOS that is called whenever the mouse sent a complete "packet" of data bytes. The BIOS needs to store the packet size and the callback function address somewhere, as well as the individual bytes received from the mouse that make up a packet. Most (all?) BIOSes use the EBDA (extended BIOS data area) at the end of the conventional RAM to store this data. As reservation of conventional RAM is done on a kilobyte granularity, PS/2 mouse support will cost a whole kilobyte of conventional RAM unless your BIOS already reserves the EBDA for some other purpose. Mainstream (AMI/Award/Phoenix) BIOS does not, but other kinds of BIOSes, e.g. the Compaq ProSignia BIOS reserve that 1KB of conventional RAM unconditionally.
Typically, Award/AMI BIOSes only enable PS/2 mouse support if (a) the BIOS configuration bits say that a PS/2-type keyboard controller is installed and (b) a PS/2 mouse is connected. Sometimes, you also have (c) the BIOS setup option "PS/2 mouse function" is set to "Enabled".
dear friend, do youhavethe schematic of this board? it seems my cpu supply is faulty.
about cache，ifI bank0 512+bank1 128， it is possible?
youxiaojie wrote on 2025-03-02, 20:54:about cache，ifI bank0 512+bank1 256， it is possible?
In dual-bank mode, both banks are interleaved and store half of each 16-byte cache line. If the banks has different sizes, you would have cache lines where half of the memory does not exist.
mkarcher wrote on 2025-03-02, 21:07:youxiaojie wrote on 2025-03-02, 20:54:about cache，ifI bank0 512+bank1 256， it is possible?
In dual-bank mode, both banks are interleaved and store half of each 16-byte cache line. If the banks has different sizes, you would have cache lines where half of the memory does not exist.
Also, the only reason I could think that you would even want to mismatch banks is one of those boards with four 32-pin sockets and four 28-pin sockets. Even if it were possible, it would be 512+128 not 512+256 (since 256KB across four chips requires 32-pin chips)
Is there any insight into why board makers did that configuration? Does omitting four pins on half the sockets really save much space?
so the 256KB cache in single bank and 128KB plus 128KB in double bank, which on is faster?
The fastest the 486 can do one of these burst reads of four 32-bit values is 2-1-1-1.
A double-bank cache is more likely to be able to keep up with that, especially above 33 MHz, because except for the first read, the inactive bank gets to see the address one cycle in advance.
The only reason for single bank is so the board vendor could save sockets and chips. For example, a lot of those barely-longer-than-an-ISA-slot boards only have four, 32-pin sockets (plus tag).
Paar wrote on 2024-03-26, 12:51:I have finished my Octek Hippo 10 mod, see pictures. Had to do a little rewiring work on the back but it works fine otherwise. I […]
I have finished my Octek Hippo 10 mod, see pictures. Had to do a little rewiring work on the back but it works fine otherwise. I'm looking forward to benchmarking it and see if it handles 40 MHz FSB properly.
dear friend, could you take a picture of this part? esp r107? my board is burnt.
