Hi magicmanred,
To start with an introduction, I’m the guy who did the patched BIOS you are using and I will try to help with testing the VRM circuit on your QDI P5MVP3/A3 board.
Looking at the photo of this board on TRW, I see the 3 main active components of this VRM right next to the lever of the CPU Socket.
The first is the RC5051M DC-DC Controller, which is the “brain” of the VRM. Right next to this IC are the 2 power FETs, that do the heavy work of this switching voltage regulator. On the TRW photo I see CEB603AL FETs, but your board revision may use another equivalent type for these transistors Q6 and Q7.
Then there are also 2 diodes D8 and D12. The silver ring on these cylindrical black components indicates the cathode, so the other side is the anode of the diode.
Other components nearby belong to the VRM as well, like 2 coil-shape inductors, 7 electrolytic capacitors, and numerous small surface-mounted resistors and capacitors.
Here are the datasheets of the Controller and the FETs:
The attachment RC5051.pdf is no longer available
The attachment CEB_CEP603AL.PDF is no longer available
Looking at the Block Diagram on the first page of the RC5051M datasheet, you get an idea of how this circuit works. Via pins 9 and 12, the controller drives the gates of the Low-side and the High-side Power FET directly. The controller alternates driving the High- and Low-side FETS to conduct, but never at the same time! 😉
The drain of the High-side FET is connected to +5V and the source of the Low-side FET is connected to GND. In the middle, the source of the High-side FET is connected to the drain of the Low-side FET and this point provides the Vcore for the CPU via an inductor-capacitor filter.
This Ouput voltage is controlled by the RC5051M via a feedback loop, and is regulated by changing the time the High- and Low-side FETs are opened/closed.
Because the FETs essentially work as current switches, they hardly have to dissipate any heat.
The required Vcore is set by the 5 VID input pins. The logic table is on page 4 of the datasheet. Usually these VID pins are driven by jumpers or dip-switches, but on this board the BIOS controls the VID lines via General Purpose Output lines of the VIA 586B Southbridge.
Note that the BIOS only controls VID0, 1, 2, and 3. VID4 is probably not connected on this board and is always high, resulting in possible Vcore settings from 2.0V to 3.5V.
Now, for the measurements it’s best to start with the regular K6-2/500 and the patch J.1 BIOS.
Set the multimeter to Volts DC and connect the black lead to a GND point like the metal casing of the Keyboard or USB port. With the red lead measure the voltage on the drain of each FET. The drain is the metal lip at the top of the FET.
On one FET you should measure +5V and the other should indicate 2.2V. The Low-side FET is the one where you measure 2.2V and its drain is your Vcore measure point.
I’m interested in any deviating values and which FET is the one that gets hot with the K6-2+.
Now change the SpeedEasy Core voltage to Manual and lower it to 2.1V. You may need to downclock the K6-2 to 400 or 300MHz to keep it working on this undervolt.
Check if the voltage on the Vcore measure point follows the SpeedEasy Vcore setting, after "SAFE & EXIT". Also try 2.0V and 2.3V.
Hopefully you find a deviation here, so we have a lead to the problem.
But when all is well, repeating these measurements with the K6-2+ installed should get us further.
Cheers, Jan